get rid of SIP_DECL() and reduce #ifdef DP83820 code. Next step
is to move a bunch of shared code to a new file (if_sipcom.c, say)
and compile it *once*.
While I am here, add suspend/resume handling to sip(4) and to
gsip(4).
Tested with the NatSemi sip(4) on the Soekris net4521. I don't
have any gsip(4) to test with, and it seems that the few holders
of gsip(4) in the world keep them in their attic, anyway.
82571 manual and Intel Application Note 450. Previously, we were setting
RADV and TIDV/TADV values that didn't make any sense given the enormous
ITR value we were setting (well outside the range recommended by Intel
and quite possibly rejected silently by the chip as junk) and setting
RADV without setting RDTR, which is explicitly documented as having no
effect.
A considerable performance improvement is achieved for TCP and UDP at
gigabit speed. I need to revisit this to deal with the timer ticks
being 4X as long when the chip's in 100mbit mode, and to set values
for the older chips' interrupt timers that are more like what the
appnote recommends. This should help for 82543 and newer, though.
- malloc(9) -> kmem(9) now that most of the bio code doesn't need to run
on interrupt context.
- Reduce code that runs in interrupt context to a small part in
arc_msgbuf() and is protected by arc_lock()/arc_unlock().
Reviewed and help by ad@.
break functionality. I've tested this on a PCIE R423 (X800).
- In drm_drv.c, check that the requested context lock matches the holder
of the lock.
- Unify radeon offset checking. (r300_cmdbuf.c, radeon_drv.h, radeon_state.c)
[Replace r300_check_offset() with generic radeon_check_offset(), which doesn't
reject valid offsets when the framebuffer area is at the very end of the card's
32 bit address space. Make radeon_check_and_fixup_offset() use
radeon_check_offset() as well.
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=7697]
NOTE: There is another AGP fix that I didn't have time to merge
that I thought might help with getting this to work on macppc.
Contact me if you're interested. Hi macallan@! ;)
radeon_cp.c, radeon_drv.h: (GIT id: bb5f2158dbd30dbbffa3881fac75b71d71ecaaf9)
- set the address to access the aperture on the CPU side correctly
[This code relied on the CPU and GPU address for the aperture being the same,
On some r5xx hardware I was playing with I noticed that this isn't always true.
I wonder if this will fix some of those r4xx DRI issues we've seen in the past.]
- Commit the ring after earch partial texture. (radeon_state.c)
(GIT ID: ac8406420ea80ffe5ccaadc1ff0124f95709a23d)
[Commit the ring after each partial texture upload blit.
This makes sure each blit starts as early as possible, which may improve
texture upload performance in some cases.]
If anyone's having any issues in particular--especially those which
can be _teased apart from AGP driver issues--please let me know
and I'll investigate. Thanks. There are also tons of fixes for the i915,
but I don't want to change too much at once.
this fixes a panic with debugging options.
- Do not use a callout to refresh sensor data, and make it available
every time someone requests it.
- Enable ENVSYS_FMONSTCHANGED for notifications in the volumes.
(nForce 2/3/4).
nfsmb(4) is now properly working on newer MCPs, tested by wiz@ on MCP55:
nfsmbc0 at pci0 dev 1 function 1: NVIDIA nForce MCP55 SMBus Controller (rev. 0xa2)
nfsmb0 at nfsmbc0 SMBus 1
iic0 at nfsmb0: I2C bus
spdmem0 at iic0 addr 0x51
spdmem0: DDR2 SDRAM memory, data ECC, 1024MB, 667MHz, PC2-5300
spdmem0: 14 rows, 10 cols, 2 ranks, 4 banks/chip, 3.00ns cycle time
spdmem0: voltage SSTL 1.8V, refresh time 7.8us (self-refreshing)
nfsmb1 at nfsmbc0 SMBus 2
iic1 at nfsmb1: I2C bus
This will not work until (at the very least) we map the memory properly
(MMIO/VRAM BARs are 64-bit)--some of the values in the configuration
space may be different. I will discuss this with others, and maybe
it will work someday.
consulted indicated that this ID is an R430 (including xf86-video-ati).
PCI_PRODUCT_ATI_RADEON_R430_554F (primary)
PCI_PRODUCT_ATI_RADEON_R430_556F (secondary)
vga0 at pci1 dev 0 function 0: ATI Technologies product 0x554f (rev. 0x00)
ATI Technologies product 0x556f (miscellaneous display) at pci1 dev 0 function 1 not configured
interrupts while attaching uhci. Fixes recent problems with uvm_fault
during uhci attach, which appear to be caused by a pending interrupt
left over from the device while it was operating in legacy support mode
under the control of the BIOS.
Patch by joerg@ because his was better than mine.
an Atheros WLAN. That generates a CB_SOCKET_EVENT_CSTS event on
the bridge. The event isn't interesting to pccbb(4), so we used
to ignore the interrupt. Now, let the child devices try to handle
the interrupt, instead. The Atheros NIC produces interrupts more
reliably, now: used to be that it would only interrupt if the driver
avoided powering down the NIC's cardslot, and then the NIC would
only work after it was reset a second time.
Let the TI1420 PCI-Cardbus bridge do burst reads from the primary
(PCI) bus. This ought to improve Tx performance on Cardbus NICs.
This optimization may apply to other TI bridges, but I only have
a datasheet for the TI1420. :-/
Activate PCI Parity Error and System Error reporting on PCI-Cardbus
bridges.
To avoid data destruction, set the Master Abort mode to 1. Stops
the bridge from silently discarding writes from the secondary bus
to the primary bus (Cardbus writes to PCI). Also, stops the bridge
from fulfilling a read by a bus master on the secondary bus that
failed on the primary bus with 0xffffffff (Cardbus reads from PCI).
Now the bus will indicate an error condition (SERR) instead of
silently destroying/corrupting data.
Forward system error indications from the secondary to the primary
bus. Detect parity errors on the secondary.
Set a Cardbus card's Latency Timer to something reasonable, according
to the Cardbus card's Minimum Grant and the bandwidth available on
the PCI bus. Restore the Latency Timer when re-enabling a card
(e.g., after power reactivation).
transaction to 8. value 32 triggers occational watchdog() Tx
timeout when higher system load. This symptom is observed in
ipforwarding across two PCI devices case so far, and it remains
unidentified what really happens for Tx DMA activity. 16 seems
ok, 8 is conservative and heuristic value. may need more adjustment
work in other parts.
http://mail-index.netbsd.org/tech-kern/2007/11/09/0001.html
sysmon_envsys_create() and sysmon_envsys_destroy() were added to
create/destroy sysmon_envsys objects (and its TAILQ/LIST for sensors/events).
sysmon_envsys_sensor_attach() and sysmon_envsys_sensor_detach() were
added to attach/detach sensors to a specified sysmon_envsys device.
The events framework is now per device and configurable via the
ENVSYS_SETDICTIONARY ioctl or /etc/envsys.conf and envstat(8).
Update all users and documentation to reflect these changes.
So far it supports some acceleration ( copies and rectangle fills ) but
no video mode programming at all.
Known problems:
- tested only on macppc
- matches only one r128 chip out of ca. 30
- character drawing is unaccelerated
- no attempt is made to restore the console when X exits
If you have a system where it doesn't get one and you still want pcic,
you can just disable cbb. This check is invalid as soon as the PCI
interrupt register is not used and broke on my Dell Latitude for that
reason.
model 9030 and 9050/9052. They work a functional bridge to host
any kind of I/O devices. The exact product type can be identified
via VPD (vital product ID) PCI configuration registers if they are
programmed by the particular PLX I/O accelerator applications.
Otherwise, it's not possible to distinguish which kind of function
is implemented inside.
operator consistent in locking macros, use mb(9) for memory barrier ops
(to be replaced with bus_space_barrier(9) at a later date; this is not
necessary for x86 but might be for e.g. mips).
More to come. Try it out! It's a lot more stable now just with the
mutex(9) changes.
- distinguish 8842 from 8841. 8842 now keeps media selection "auto"
and indicates "up 100baseTX-FDX flow" when either of two ports has
a valid link. There is no provision to see and control the two this
moment and their media selections remain in "auto" all the time. This
arrangement is considered acceptable since 8842's external ports are
connected with the internal EMAC via managed 3 port Ethernet switch.
- 8841 behaves a plain stanadrd 10/100 EMAC with standard media
selection feature.
- gather MIB statistics counter values with evcnt(8) framework.
- increase Tx/Rx DMA DMA burst transfer size from 16 to 32.
Next attempt at trying to fix the irregular interrupt storms on my
Thinkpad: when we find a PCI Express device, check the list of
notification events and if any are sets, clear them. We can't handle
them ATM anyway.
No functionality change intented.
IHAE "IP Header Alignment Enable" feature of RXC register;
- careful cross referencing at KSZ8692P/8841P/8842P PDFs indicates IHEA
bit works as follows; When the feature is turned on, Rx DMA engine
will populate Rx frame data in the Rx memory with +2 or +3 byte swifted
to make its IP head field 32bit aligned. The shift amount is recorded
inside RDES0 to tell 0, 2 or 3. The automatic alignment is done only
when IHAE is enabled _and_ the Rx frame was IP frame. In other cases,
RDES0 swift amount field keeps 0.
- KSZ8841P document mentions the IHAE bit but its reference link is broken
to tell the new RDES0 field. KSZ8842P lacks both. The bit usage of
RDES0 23:20 seems different from KSZ8692P, which brings me a vague
suspiction of documentation error.
1) Move a magic number writing code.
Fix a watchdog timeout and "block failed to stop" problem on BCM5701 B5 card.
2) Fix incorrect register write.
Fix a watchdog timeout "block failed to stop" problem on BCM5700 B2 card.
3) Wait more long time for PCISTATE register to return to its original
pre-reset state.
Fix "pcistate failed to revert" problem on BCM5703 A2 card.
which expects a properly filled mbuf chain, but bus_dmamap_load for the
mbuf storage space instead.
- If the chip supports jumbo frames
+ keep track of which RX descriptor uses which jumbo mbuf buffer, so
that we can rewrite the physaddr field of the descriptor later, as it
might be partially overwritten by the hw
+ when we're out of jumbo mbufs, and if the packet is small enough,
copy it into a cluster mbuf
Those changes make my nfe(4) stable in both cases (defining NFE_NO_JUMBO
for the first one).
In nfe_start() do a fast return if IFF_OACTIVE is set, in
this case we need a Tx interrupt to clean up the DMA ring
before if_start can be properly called.
"Add support for Realtek ALC883. This is the "value" edition of the
ALC882, and differs only by lacking an ADC and a mixer, so have it use
ALC882's get_port(), set_port() and a slightly modified version of its
mixer init."
Keep track of the status of the scan.
On a transition IEEE80211_S_SCAN -> IEEE80211_S_SCAN, don't stop the previous
scan, finish the current scan.
When we receive some frames in the IEEE80211_S_SCAN state, set current_channel
based on the value advertised in beacons or probre reponse.
Moreover, it fixes WPA issues for me.
This does NOT identify the devices, merely indicates the
presence of devices at certain addresses. Tested on ichsmb
and nfsmb - other SMBus devices will need to ensure the
proper bus type is set. (I2C_TYPE_SMBUS)
From Nicolas Joly, via Paul Goyette, in PR#36744.
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_ec) :
ether_delmulti(ifr, &sc->sc_ec);
if (error == ENETRESET) {
to this,
if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
which does the same thing.
(A bazillion is a very large number. This seems to make the i386
ALL kernel smaller by 3kB to 4kB.)
Use ifreq_getaddr() twice in es(4).
Whitespace nits.
identify sockaddr_dl abuse that remains in the kernel, especially
the potential for overwriting memory past the end of a sockaddr_dl
with, e.g., memcpy(LLADDR(), ...).
especially the Bridge Control Register definition, instead of
rolling its own.
As we read/modify/write configuration registers, use a variable
that is named for the register we're r/m/w'ing, instead of using
the variable 'reg' over and over. This helps both a human reader
verify that we're not reading register X, modifying it, and writing
back to register Y (oops); the compiler can help a little by warning
that a variable is used before it is initialized.
need to understand the locking around that field. Instead of setting
B_ERROR, set b_error instead. b_error is 'owned' by whoever completes
the I/O request.
OpenBSD).
While here, remove some dead code I added when I ported the code from OpenBSD.
IMPORTANT : You must download the 2.14.4 firmware or update your
sysutils/wpi-firmware2 to the last revision (2.14.4) or the driver will stop
working.
1/ Update the driver to use the new firmware images from Intel (2.14.3.)
2/ Read the list of supported channels from the EEPROM instead of having
it hard-coded in the driver.
3/ Limit output power to what is specified in EEPROM.
4/ Decrease output power for highest OFDM rates to reduce distortion.
5/ Automatically adjust output power to temperature changes for increased
throughput and range.
6/ Attach the adapter's onboard thermal sensor to the sensor framework.
7/ Replace 'magic' fields in structures with their correct definitions.
8/ Rewrite the firmware load in order to reduce the diff with OpenBSD one
NOTE2: you must install sysutils/wpi-firmware2 in order to use the new
driver
NOTE2: if you are using a channel not allowed by the regulatory domain
of your adapter, you will no longer be able to associate.
Thanks a lot for his hard work to damien@OpenBSD.org
dyoung