Improve Cardbus performance, error handling, and error reporting.
Let the TI1420 PCI-Cardbus bridge do burst reads from the primary (PCI) bus. This ought to improve Tx performance on Cardbus NICs. This optimization may apply to other TI bridges, but I only have a datasheet for the TI1420. :-/ Activate PCI Parity Error and System Error reporting on PCI-Cardbus bridges. To avoid data destruction, set the Master Abort mode to 1. Stops the bridge from silently discarding writes from the secondary bus to the primary bus (Cardbus writes to PCI). Also, stops the bridge from fulfilling a read by a bus master on the secondary bus that failed on the primary bus with 0xffffffff (Cardbus reads from PCI). Now the bus will indicate an error condition (SERR) instead of silently destroying/corrupting data. Forward system error indications from the secondary to the primary bus. Detect parity errors on the secondary. Set a Cardbus card's Latency Timer to something reasonable, according to the Cardbus card's Minimum Grant and the bandwidth available on the PCI bus. Restore the Latency Timer when re-enabling a card (e.g., after power reactivation).
This commit is contained in:
dyoung
parent
3537e99eb1
commit
43d2148e33
@ -1,4 +1,4 @@
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/* $NetBSD: cardbus.c,v 1.76 2007/10/19 11:59:38 ad Exp $ */
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/* $NetBSD: cardbus.c,v 1.77 2007/11/16 18:36:52 dyoung Exp $ */
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/*
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* Copyright (c) 1997, 1998, 1999 and 2000
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@ -33,7 +33,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cardbus.c,v 1.76 2007/10/19 11:59:38 ad Exp $");
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__KERNEL_RCSID(0, "$NetBSD: cardbus.c,v 1.77 2007/11/16 18:36:52 dyoung Exp $");
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#include "opt_cardbus.h"
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@ -122,12 +122,12 @@ cardbusattach(struct device *parent, struct device *self, void *aux)
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sc->sc_bus = cba->cba_bus;
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sc->sc_intrline = cba->cba_intrline;
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sc->sc_cacheline = cba->cba_cacheline;
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sc->sc_lattimer = cba->cba_lattimer;
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sc->sc_max_lattimer = MIN(0xf8, cba->cba_max_lattimer);
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printf(": bus %d", sc->sc_bus);
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if (bootverbose)
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printf(" cacheline 0x%x, lattimer 0x%x", sc->sc_cacheline,
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sc->sc_lattimer);
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sc->sc_max_lattimer);
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printf("\n");
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sc->sc_iot = cba->cba_iot; /* CardBus I/O space tag */
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@ -194,7 +194,7 @@ cardbus_read_tuples(struct cardbus_attach_args *ca, cardbusreg_t cis_ptr,
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DPRINTF(("%s: reading CIS data from ROM\n",
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sc->sc_dev.dv_xname));
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} else {
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reg = CARDBUS_BASE0_REG + (cardbus_space - 1) * 4;
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reg = CARDBUS_CIS_ASI_BAR(cardbus_space);
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DPRINTF(("%s: reading CIS data from BAR%d\n",
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sc->sc_dev.dv_xname, cardbus_space - 1));
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}
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@ -258,8 +258,10 @@ cardbus_read_tuples(struct cardbus_attach_args *ca, cardbusreg_t cis_ptr,
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CARDBUS_COMMAND_STATUS_REG,
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command | CARDBUS_COMMAND_MEM_ENABLE);
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/* XXX byte order? */
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printf("%s: ding!\n", __func__);
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bus_space_read_region_1(ca->ca_memt, bar_memh,
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cis_ptr, tuples, MIN(bar_size, len));
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printf("%s: dong!\n", __func__);
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found++;
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}
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command = cardbus_conf_read(cc, cf, tag,
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@ -415,7 +417,7 @@ cardbus_rescan(struct device *self, const char *ifattr,
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cardbus_function_tag_t cf;
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cardbustag_t tag;
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cardbusreg_t id, class, cis_ptr;
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cardbusreg_t bhlc;
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cardbusreg_t bhlc, icr, lattimer;
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int cdstatus;
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int function, nfunction;
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struct device *csc;
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@ -442,6 +444,9 @@ cardbus_rescan(struct device *self, const char *ifattr,
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/*
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* Wait until power comes up. Maxmum 500 ms.
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*
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* XXX What is this for? The bridge driver ought to have waited
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* XXX already.
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*/
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{
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int i;
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@ -509,27 +514,39 @@ cardbus_rescan(struct device *self, const char *ifattr,
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/* set initial latency and cacheline size */
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bhlc = cardbus_conf_read(cc, cf, tag, CARDBUS_BHLC_REG);
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DPRINTF(("%s func%d bhlc 0x%08x -> ", sc->sc_dev.dv_xname,
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function, bhlc));
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bhlc &= ~((CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT) |
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(CARDBUS_CACHELINE_MASK << CARDBUS_CACHELINE_SHIFT));
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icr = cardbus_conf_read(cc, cf, tag, CARDBUS_INTERRUPT_REG);
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DPRINTF(("%s func%d icr 0x%08x bhlc 0x%08x -> ",
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device_xname(&sc->sc_dev), function, icr, bhlc));
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bhlc &= ~(CARDBUS_CACHELINE_MASK << CARDBUS_CACHELINE_SHIFT);
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bhlc |= (sc->sc_cacheline & CARDBUS_CACHELINE_MASK) <<
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CARDBUS_CACHELINE_SHIFT;
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bhlc |= (sc->sc_lattimer & CARDBUS_LATTIMER_MASK) <<
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CARDBUS_LATTIMER_SHIFT;
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/*
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* Set the initial value of the Latency Timer.
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*
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* While a PCI device owns the bus, its Latency
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* Timer counts down bus cycles from its initial
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* value to 0. Minimum Grant tells for how long
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* the device wants to own the bus once it gets
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* access, in units of 250ns.
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*
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* On a 33 MHz bus, there are 8 cycles per 250ns.
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* So I multiply the Minimum Grant by 8 to find
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* out the initial value of the Latency Timer.
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*
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* Avoid setting a Latency Timer less than 0x10,
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* since the old code did not do that.
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*/
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lattimer =
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MIN(sc->sc_max_lattimer, MAX(0x10, 8 * PCI_MIN_GNT(icr)));
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if (PCI_LATTIMER(bhlc) < lattimer) {
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bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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bhlc |= (lattimer << PCI_LATTIMER_SHIFT);
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}
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cardbus_conf_write(cc, cf, tag, CARDBUS_BHLC_REG, bhlc);
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bhlc = cardbus_conf_read(cc, cf, tag, CARDBUS_BHLC_REG);
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DPRINTF(("0x%08x\n", bhlc));
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if (CARDBUS_LATTIMER(bhlc) < 0x10) {
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bhlc &= ~(CARDBUS_LATTIMER_MASK <<
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CARDBUS_LATTIMER_SHIFT);
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bhlc |= (0x10 << CARDBUS_LATTIMER_SHIFT);
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cardbus_conf_write(cc, cf, tag,
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CARDBUS_BHLC_REG, bhlc);
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}
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/*
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* We need to allocate the ct here, since we might
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* need it when reading the CIS
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@ -539,6 +556,7 @@ cardbus_rescan(struct device *self, const char *ifattr,
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panic("no room for cardbus_tag");
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}
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ct->ct_bhlc = bhlc;
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ct->ct_cc = sc->sc_cc;
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ct->ct_cf = sc->sc_cf;
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ct->ct_bus = sc->sc_bus;
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@ -763,6 +781,7 @@ cardbus_function_enable(struct cardbus_softc *sc, int func)
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{
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cardbus_chipset_tag_t cc = sc->sc_cc;
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cardbus_function_tag_t cf = sc->sc_cf;
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cardbus_devfunc_t ct;
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cardbusreg_t command;
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cardbustag_t tag;
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@ -783,6 +802,9 @@ cardbus_function_enable(struct cardbus_softc *sc, int func)
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cardbus_conf_write(cc, cf, tag, CARDBUS_COMMAND_STATUS_REG, command);
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if ((ct = sc->sc_funcs[func]) != NULL)
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Cardbus_conf_write(ct, tag, CARDBUS_BHLC_REG, ct->ct_bhlc);
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cardbus_free_tag(cc, cf, tag);
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DPRINTF(("%x\n", sc->sc_poweron_func));
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@ -1,4 +1,4 @@
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/* $NetBSD: cardbusvar.h,v 1.35 2005/12/11 12:21:15 christos Exp $ */
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/* $NetBSD: cardbusvar.h,v 1.36 2007/11/16 18:36:53 dyoung Exp $ */
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/*
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* Copyright (c) 1998, 1999 and 2000
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@ -127,7 +127,7 @@ typedef struct cardbus_functions {
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#endif /* rbus */
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/*
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* struct cbslot_attach_args is the attach argument for cardbus card.
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* struct cbslot_attach_args is the attach argument for Cardbus cardslot.
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*/
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struct cbslot_attach_args {
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const char *cba_busname;
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@ -147,7 +147,17 @@ struct cbslot_attach_args {
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#endif
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int cba_cacheline; /* cache line size */
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int cba_lattimer; /* latency timer */
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int cba_max_lattimer; /* No card's latency timer may
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* exceed this. On a PCI-Cardbus
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* bridge, I let the latency timer on
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* the primary bus (PCI bus) set
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* the maximum. That is kind of an
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* arbitrary choice. A more sensible
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* choice may be either the
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* latency timer on the primary bus,
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* or the bridge's buffer size,
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* whichever is larger.
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*/
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};
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@ -175,7 +185,12 @@ struct cardbus_softc {
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#endif
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int sc_cacheline; /* cache line size */
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int sc_lattimer; /* latency timer */
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int sc_max_lattimer; /* No card's latency timer
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* may exceed this. On a PCI-Cardbus
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* bridge, the latency timer on
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* the primary bus (PCI bus) sets
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* the maximum.
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*/
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int sc_volt; /* applied Vcc voltage */
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#define PCCARD_33V 0x02
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#define PCCARD_XXV 0x04
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@ -204,8 +219,8 @@ typedef struct cardbus_devfunc {
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rbus_tag_t ct_rbus_memt; /* CardBus mem rbus tag */
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#endif
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u_int32_t ct_bar[6]; /* Base Address Regs 0 to 6 */
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u_int32_t ct_lc; /* Latency timer and cache line size */
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cardbusreg_t ct_bar[6]; /* Base Address Regs 0 to 6 */
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cardbusreg_t ct_bhlc; /* Latency timer and cache line size */
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/* u_int32_t ct_cisreg; */ /* CIS reg: is it needed??? */
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struct device *ct_device; /* pointer to the device */
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@ -1,4 +1,4 @@
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/* $NetBSD: pccbb.c,v 1.150 2007/10/25 13:49:06 joerg Exp $ */
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/* $NetBSD: pccbb.c,v 1.151 2007/11/16 18:36:51 dyoung Exp $ */
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/*
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* Copyright (c) 1998, 1999 and 2000
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@ -31,7 +31,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.150 2007/10/25 13:49:06 joerg Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pccbb.c,v 1.151 2007/11/16 18:36:51 dyoung Exp $");
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/*
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#define CBB_DEBUG
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@ -93,6 +93,8 @@ struct cfdriver cbb_cd = {
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#define STATIC static
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#endif
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int pccbb_burstup = 1;
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/*
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* delay_ms() is wait in milliseconds. It should be used instead
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* of delay() if you want to wait more than 1 ms.
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@ -312,7 +314,7 @@ const struct yenta_chipinfo {
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PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
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{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX,
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PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
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{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX,
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{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI1420,
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PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
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{ MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X,
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PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
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@ -683,12 +685,12 @@ pccbb_pci_callback(struct device *self)
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#endif
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cba.cba_cacheline = PCI_CACHELINE(bhlc);
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cba.cba_lattimer = PCI_LATTIMER(bhlc);
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cba.cba_max_lattimer = PCI_LATTIMER(bhlc);
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if (bootverbose) {
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printf("%s: cacheline 0x%x lattimer 0x%x\n",
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sc->sc_dev.dv_xname, cba.cba_cacheline,
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cba.cba_lattimer);
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cba.cba_max_lattimer);
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printf("%s: bhlc 0x%x\n",
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device_xname(&sc->sc_dev), bhlc);
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}
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@ -738,8 +740,8 @@ pccbb_chipinit(struct pccbb_softc *sc)
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pcitag_t tag = sc->sc_tag;
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bus_space_tag_t bmt = sc->sc_base_memt;
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bus_space_handle_t bmh = sc->sc_base_memh;
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pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, slotctl, sockctl, sockmask,
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sysctrl;
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pcireg_t bcr, bhlc, cbctl, csr, lscp, mfunc, mrburst, slotctl, sockctl,
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sockmask, sysctrl;
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/*
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* Set PCI command reg.
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@ -749,6 +751,7 @@ pccbb_chipinit(struct pccbb_softc *sc)
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/* I believe it is harmless. */
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csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
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PCI_COMMAND_MASTER_ENABLE);
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csr |= (PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE);
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pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
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/*
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@ -782,6 +785,12 @@ pccbb_chipinit(struct pccbb_softc *sc)
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bcr |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
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/* assert reset */
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bcr |= PCI_BRIDGE_CONTROL_SECBR << PCI_BRIDGE_CONTROL_SHIFT;
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/* Set master abort mode to 1, forward SERR# from secondary
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* to primary, and detect parity errors on secondary.
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*/
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bcr |= PCI_BRIDGE_CONTROL_MABRT << PCI_BRIDGE_CONTROL_SHIFT;
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bcr |= PCI_BRIDGE_CONTROL_SERR << PCI_BRIDGE_CONTROL_SHIFT;
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bcr |= PCI_BRIDGE_CONTROL_PERE << PCI_BRIDGE_CONTROL_SHIFT;
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pci_conf_write(pc, tag, PCI_BRIDGE_CONTROL_REG, bcr);
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switch (sc->sc_chipset) {
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@ -797,6 +806,28 @@ pccbb_chipinit(struct pccbb_softc *sc)
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pci_conf_write(pc, tag, PCI_CBCTRL, cbctl);
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break;
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case CB_TI1420:
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sysctrl = pci_conf_read(pc, tag, PCI_SYSCTRL);
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mrburst = pccbb_burstup
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? PCI1420_SYSCTRL_MRBURST : PCI1420_SYSCTRL_MRBURSTDN;
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if ((sysctrl & PCI1420_SYSCTRL_MRBURST) == mrburst) {
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printf("%s: %swrite bursts enabled\n",
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device_xname(&sc->sc_dev),
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pccbb_burstup ? "read/" : "");
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} else if (pccbb_burstup) {
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printf("%s: enabling read/write bursts\n",
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device_xname(&sc->sc_dev));
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sysctrl |= PCI1420_SYSCTRL_MRBURST;
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pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
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} else {
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printf("%s: disabling read bursts, "
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"enabling write bursts\n",
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device_xname(&sc->sc_dev));
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sysctrl |= PCI1420_SYSCTRL_MRBURSTDN;
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sysctrl &= ~PCI1420_SYSCTRL_MRBURSTUP;
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pci_conf_write(pc, tag, PCI_SYSCTRL, sysctrl);
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}
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/*FALLTHROUGH*/
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case CB_TI12XX:
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/*
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* Some TI 12xx (and [14][45]xx) based pci cards
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@ -1,4 +1,4 @@
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/* $NetBSD: pccbbreg.h,v 1.12 2007/08/11 00:31:05 dyoung Exp $ */
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/* $NetBSD: pccbbreg.h,v 1.13 2007/11/16 18:36:52 dyoung Exp $ */
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/*
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* Copyright (c) 1999 HAYAKAWA Koichi. All rights reserved.
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*
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@ -131,6 +131,13 @@
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#define PCI12XX_CBCTRL_SPK_ENA 0x0200 /* Speaker enable */
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#define PCI12XX_CBCTRL_INTR_DET 0x0100 /* functional interrupt detect */
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/* 1: permit burst read from CardBus (default: on) */
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#define PCI1420_SYSCTRL_MRBURSTDN __BIT(15)
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/* 1: permit burst read from PCI bus (default: off!) */
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#define PCI1420_SYSCTRL_MRBURSTUP __BIT(14)
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#define PCI1420_SYSCTRL_MRBURST \
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(PCI1420_SYSCTRL_MRBURSTDN|PCI1420_SYSCTRL_MRBURSTUP)
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/* PCI_BCR_INTR additional bit for Rx5C46[567] */
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#define CB_BCRI_RL_3E0_ENA 0x08000000
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