Add support agp_amd64. Imported from FreeBSD.
This commit is contained in:
kiyohara
parent
a39089a88a
commit
e42d8a086d
@ -1,4 +1,4 @@
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/* $NetBSD: agp.c,v 1.46 2007/03/06 01:09:42 xtraeme Exp $ */
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/* $NetBSD: agp.c,v 1.47 2007/08/04 09:33:05 kiyohara Exp $ */
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/*-
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* Copyright (c) 2000 Doug Rabson
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@ -65,7 +65,7 @@
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.46 2007/03/06 01:09:42 xtraeme Exp $");
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__KERNEL_RCSID(0, "$NetBSD: agp.c,v 1.47 2007/08/04 09:33:05 kiyohara Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -110,6 +110,7 @@ static int agpdev_match(struct pci_attach_args *);
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#include "agp_intel.h"
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#include "agp_sis.h"
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#include "agp_via.h"
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#include "agp_amd64.h"
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const struct agp_product {
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uint32_t ap_vendor;
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@ -171,6 +172,27 @@ const struct agp_product {
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NULL, agp_via_attach },
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#endif
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#if NAGP_AMD64 > 0
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{ PCI_VENDOR_AMD, PCI_PRODUCT_AMD_AGP8151_DEV,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_755,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_760,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_PCHB,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8M800_0,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8T890_0,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB_0,
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agp_amd64_match, agp_amd64_attach },
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{ PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_K8HTB,
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agp_amd64_match, agp_amd64_attach },
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#endif
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{ 0, 0,
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NULL, NULL },
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};
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541
sys/dev/pci/agp_amd64.c
Normal file
541
sys/dev/pci/agp_amd64.c
Normal file
@ -0,0 +1,541 @@
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/*-
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* Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: agp_amd64.c,v 1.1 2007/08/04 09:33:05 kiyohara Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/proc.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/lock.h>
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#include <sys/agpio.h>
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#include <uvm/uvm_extern.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/agpvar.h>
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#include <dev/pci/agpreg.h>
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#include <dev/pci/pcidevs.h>
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#include <machine/bus.h>
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#define AMD64_MAX_MCTRL 8
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/* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
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#define AGP_AMD64_NVIDIA_PCITAG(pc) pci_make_tag(pc, 0, 11, 0)
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/* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
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#define AGP_AMD64_VIA_PCITAG(pc) pci_make_tag(pc, 0, 1, 0)
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static uint32_t agp_amd64_get_aperture(struct agp_softc *);
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static int agp_amd64_set_aperture(struct agp_softc *, uint32_t);
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static int agp_amd64_bind_page(struct agp_softc *, off_t, bus_addr_t);
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static int agp_amd64_unbind_page(struct agp_softc *, off_t);
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static void agp_amd64_flush_tlb(struct agp_softc *);
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static void agp_amd64_apbase_fixup(struct agp_softc *);
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static void agp_amd64_uli_init(struct agp_softc *);
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static int agp_amd64_uli_set_aperture(struct agp_softc *, uint32_t);
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static int agp_amd64_nvidia_match(const struct pci_attach_args *, uint16_t);
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static void agp_amd64_nvidia_init(struct agp_softc *);
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static int agp_amd64_nvidia_set_aperture(struct agp_softc *, uint32_t);
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static int agp_amd64_via_match(const struct pci_attach_args *);
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static void agp_amd64_via_init(struct agp_softc *);
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static int agp_amd64_via_set_aperture(struct agp_softc *, uint32_t);
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struct agp_amd64_softc {
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uint32_t initial_aperture;
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struct agp_gatt *gatt;
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uint32_t apbase;
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pcitag_t ctrl_tag; /* use NVIDIA and VIA */
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pcitag_t mctrl_tag[AMD64_MAX_MCTRL];
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int n_mctrl;
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int via_agp;
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};
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static struct agp_methods agp_amd64_methods = {
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agp_amd64_get_aperture,
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agp_amd64_set_aperture,
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agp_amd64_bind_page,
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agp_amd64_unbind_page,
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agp_amd64_flush_tlb,
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agp_generic_enable,
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agp_generic_alloc_memory,
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agp_generic_free_memory,
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agp_generic_bind_memory,
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agp_generic_unbind_memory,
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};
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int
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agp_amd64_match(const struct pci_attach_args *pa)
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{
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switch (PCI_VENDOR(pa->pa_id)) {
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case PCI_VENDOR_AMD:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_AMD_AGP8151_DEV:
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return 1;
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}
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break;
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case PCI_VENDOR_SIS:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_SIS_755:
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case PCI_PRODUCT_SIS_760:
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return 1;
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}
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break;
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case PCI_VENDOR_ALI:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_ALI_M1689:
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return 1;
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}
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break;
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case PCI_VENDOR_NVIDIA:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_NVIDIA_NFORCE3_PCHB:
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return agp_amd64_nvidia_match(pa,
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PCI_PRODUCT_NVIDIA_NFORCE3_PPB2);
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/* NOTREACHED */
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case PCI_PRODUCT_NVIDIA_NFORCE3_250_PCHB:
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return agp_amd64_nvidia_match(pa,
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PCI_PRODUCT_NVIDIA_NFORCE3_250_AGP);
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/* NOTREACHED */
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}
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break;
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case PCI_VENDOR_VIATECH:
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_VIATECH_K8M800_0:
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case PCI_PRODUCT_VIATECH_K8T890_0:
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case PCI_PRODUCT_VIATECH_K8HTB_0:
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case PCI_PRODUCT_VIATECH_K8HTB:
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return 1;
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}
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break;
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}
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return 0;
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}
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static int
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agp_amd64_nvidia_match(const struct pci_attach_args *pa, uint16_t devid)
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{
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pcitag_t tag;
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pcireg_t reg;
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tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
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reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
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if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
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PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
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return 0;
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reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
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if (PCI_VENDOR(reg) != PCI_VENDOR_NVIDIA || PCI_PRODUCT(reg) != devid)
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return 0;
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return 1;
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}
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static int
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agp_amd64_via_match(const struct pci_attach_args *pa)
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{
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pcitag_t tag;
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pcireg_t reg;
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tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
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reg = pci_conf_read(pa->pa_pc, tag, PCI_CLASS_REG);
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if (PCI_CLASS(reg) != PCI_CLASS_BRIDGE ||
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PCI_SUBCLASS(reg) != PCI_SUBCLASS_BRIDGE_PCI)
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return 0;
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reg = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
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if (PCI_VENDOR(reg) != PCI_VENDOR_VIATECH ||
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PCI_PRODUCT(reg) != PCI_PRODUCT_VIATECH_K8HTB_AGP)
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return 0;
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return 1;
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}
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int
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agp_amd64_attach(struct device *parent, struct device *self, void *aux)
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{
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struct agp_softc *sc = (void *)self;
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struct agp_amd64_softc *asc;
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struct pci_attach_args *pa = aux;
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struct agp_gatt *gatt;
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pcitag_t tag;
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pcireg_t id, attbase, apctrl;
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int maxdevs, i, n;
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asc = malloc(sizeof(struct agp_amd64_softc), M_AGP, M_NOWAIT | M_ZERO);
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if (asc == NULL) {
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aprint_error(": can't allocate softc\n");
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return ENOMEM;
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}
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if (agp_map_aperture(pa, sc, AGP_APBASE) != 0) {
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aprint_error(": can't map aperture\n");
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free(asc, M_AGP);
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return ENXIO;
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}
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maxdevs = pci_bus_maxdevs(pa->pa_pc, 0);
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for (i = 0, n = 0; i < maxdevs && n < AMD64_MAX_MCTRL; i++) {
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tag = pci_make_tag(pa->pa_pc, 0, i, 3);
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id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG);
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if (PCI_VENDOR(id) == PCI_VENDOR_AMD &&
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PCI_PRODUCT(id) == PCI_PRODUCT_AMD_AMD64_MISC) {
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asc->mctrl_tag[n] = tag;
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n++;
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}
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}
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if (n == 0)
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return ENXIO;
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asc->n_mctrl = n;
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aprint_normal(": %d Miscellaneous Control unit(s) found.\n",
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asc->n_mctrl);
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aprint_normal("%s", sc->as_dev.dv_xname);
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sc->as_chipc = asc;
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sc->as_methods = &agp_amd64_methods;
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pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_AGP, &sc->as_capoff,
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NULL);
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asc->initial_aperture = AGP_GET_APERTURE(sc);
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for (;;) {
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gatt = agp_alloc_gatt(sc);
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if (gatt)
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break;
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/*
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* Probably contigmalloc failure. Try reducing the
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* aperture so that the gatt size reduces.
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*/
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if (AGP_SET_APERTURE(sc, AGP_GET_APERTURE(sc) / 2)) {
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agp_generic_detach(sc);
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return ENOMEM;
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}
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}
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asc->gatt = gatt;
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switch (PCI_VENDOR(sc->as_id)) {
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case PCI_VENDOR_ALI:
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agp_amd64_uli_init(sc);
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if (agp_amd64_uli_set_aperture(sc, asc->initial_aperture))
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return ENXIO;
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break;
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case PCI_VENDOR_NVIDIA:
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asc->ctrl_tag = AGP_AMD64_NVIDIA_PCITAG(pa->pa_pc);
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agp_amd64_nvidia_init(sc);
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if (agp_amd64_nvidia_set_aperture(sc, asc->initial_aperture))
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return ENXIO;
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break;
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case PCI_VENDOR_VIATECH:
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asc->via_agp = agp_amd64_via_match(pa);
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if (asc->via_agp) {
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asc->ctrl_tag = AGP_AMD64_VIA_PCITAG(pa->pa_pc);
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agp_amd64_via_init(sc);
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if (agp_amd64_via_set_aperture(sc,
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asc->initial_aperture))
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return ENXIO;
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}
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break;
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}
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/* Install the gatt and enable aperture. */
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attbase = (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK;
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for (i = 0; i < asc->n_mctrl; i++) {
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pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_ATTBASE,
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attbase);
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apctrl = pci_conf_read(pa->pa_pc, asc->mctrl_tag[i],
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AGP_AMD64_APCTRL);
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apctrl |= AGP_AMD64_APCTRL_GARTEN;
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apctrl &=
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~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO);
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pci_conf_write(pa->pa_pc, asc->mctrl_tag[i], AGP_AMD64_APCTRL,
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apctrl);
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}
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agp_flush_cache();
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return 0;
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}
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static uint32_t agp_amd64_table[] = {
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0x02000000, /* 32 MB */
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0x04000000, /* 64 MB */
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0x08000000, /* 128 MB */
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0x10000000, /* 256 MB */
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0x20000000, /* 512 MB */
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0x40000000, /* 1024 MB */
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0x80000000, /* 2048 MB */
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};
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#define AGP_AMD64_TABLE_SIZE \
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(sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
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static uint32_t
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agp_amd64_get_aperture(struct agp_softc *sc)
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{
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struct agp_amd64_softc *asc = sc->as_chipc;
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uint32_t i;
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i = (pci_conf_read(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL) &
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AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
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if (i >= AGP_AMD64_TABLE_SIZE)
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return 0;
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return agp_amd64_table[i];
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}
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static int
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agp_amd64_set_aperture(struct agp_softc *sc, uint32_t aperture)
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{
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struct agp_amd64_softc *asc = sc->as_chipc;
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uint32_t i;
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pcireg_t apctrl;
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int j;
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for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
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if (agp_amd64_table[i] == aperture)
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break;
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if (i >= AGP_AMD64_TABLE_SIZE)
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return EINVAL;
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for (j = 0; j < asc->n_mctrl; j++) {
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apctrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[0],
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AGP_AMD64_APCTRL);
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pci_conf_write(sc->as_pc, asc->mctrl_tag[0], AGP_AMD64_APCTRL,
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(apctrl & ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1));
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}
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switch (PCI_VENDOR(sc->as_id)) {
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case PCI_VENDOR_ALI:
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return agp_amd64_uli_set_aperture(sc, aperture);
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break;
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case PCI_VENDOR_NVIDIA:
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return agp_amd64_nvidia_set_aperture(sc, aperture);
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break;
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case PCI_VENDOR_VIATECH:
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if (asc->via_agp)
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return agp_amd64_via_set_aperture(sc, aperture);
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break;
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}
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return 0;
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}
|
||||
|
||||
static int
|
||||
agp_amd64_bind_page(struct agp_softc *sc, off_t offset, bus_addr_t physical)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
|
||||
if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return EINVAL;
|
||||
|
||||
asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
|
||||
(physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_unbind_page(struct agp_softc *sc, off_t offset)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
|
||||
if (offset < 0 || offset >= (asc->gatt->ag_entries << AGP_PAGE_SHIFT))
|
||||
return EINVAL;
|
||||
|
||||
asc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
agp_amd64_flush_tlb(struct agp_softc *sc)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
pcireg_t cachectrl;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < asc->n_mctrl; i++) {
|
||||
cachectrl = pci_conf_read(sc->as_pc, asc->mctrl_tag[i],
|
||||
AGP_AMD64_CACHECTRL);
|
||||
pci_conf_write(sc->as_pc, asc->mctrl_tag[i],
|
||||
AGP_AMD64_CACHECTRL,
|
||||
cachectrl | AGP_AMD64_CACHECTRL_INVGART);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
agp_amd64_apbase_fixup(struct agp_softc *sc)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
uint32_t apbase;
|
||||
int i;
|
||||
|
||||
apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_APBASE);
|
||||
asc->apbase = PCI_MAPREG_MEM_ADDR(apbase);
|
||||
apbase = (asc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
|
||||
for (i = 0; i < asc->n_mctrl; i++)
|
||||
pci_conf_write(sc->as_pc, asc->mctrl_tag[i], AGP_AMD64_APBASE,
|
||||
apbase);
|
||||
}
|
||||
|
||||
static void
|
||||
agp_amd64_uli_init(struct agp_softc *sc)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
pcireg_t apbase;
|
||||
|
||||
agp_amd64_apbase_fixup(sc);
|
||||
apbase = pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE);
|
||||
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_APBASE,
|
||||
(apbase & 0x0000000f) | asc->apbase);
|
||||
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_HTT_FEATURE,
|
||||
asc->apbase);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_uli_set_aperture(struct agp_softc *sc, uint32_t aperture)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
|
||||
switch (aperture) {
|
||||
case 0x02000000: /* 32 MB */
|
||||
case 0x04000000: /* 64 MB */
|
||||
case 0x08000000: /* 128 MB */
|
||||
case 0x10000000: /* 256 MB */
|
||||
break;
|
||||
default:
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_ULI_ENU_SCR,
|
||||
asc->apbase + aperture - 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
agp_amd64_nvidia_init(struct agp_softc *sc)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
pcireg_t apbase;
|
||||
|
||||
agp_amd64_apbase_fixup(sc);
|
||||
apbase =
|
||||
pci_conf_read(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE);
|
||||
pci_conf_write(sc->as_pc, sc->as_tag, AGP_AMD64_NVIDIA_0_APBASE,
|
||||
(apbase & 0x0000000f) | asc->apbase);
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE1,
|
||||
asc->apbase);
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APBASE2,
|
||||
asc->apbase);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_nvidia_set_aperture(struct agp_softc *sc, uint32_t aperture)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
uint32_t apsize;
|
||||
|
||||
switch (aperture) {
|
||||
case 0x02000000: apsize = 0x0f; break; /* 32 MB */
|
||||
case 0x04000000: apsize = 0x0e; break; /* 64 MB */
|
||||
case 0x08000000: apsize = 0x0c; break; /* 128 MB */
|
||||
case 0x10000000: apsize = 0x08; break; /* 256 MB */
|
||||
case 0x20000000: apsize = 0x00; break; /* 512 MB */
|
||||
default:
|
||||
return EINVAL;
|
||||
}
|
||||
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APSIZE,
|
||||
(pci_conf_read(sc->as_pc, asc->ctrl_tag,
|
||||
AGP_AMD64_NVIDIA_1_APSIZE) & 0xfffffff0) | apsize);
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT1,
|
||||
asc->apbase + aperture - 1);
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP_AMD64_NVIDIA_1_APLIMIT2,
|
||||
asc->apbase + aperture - 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
agp_amd64_via_init(struct agp_softc *sc)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
|
||||
agp_amd64_apbase_fixup(sc);
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE,
|
||||
asc->gatt->ag_physical);
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_GARTCTRL,
|
||||
pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_ATTBASE) | 0x180);
|
||||
}
|
||||
|
||||
static int
|
||||
agp_amd64_via_set_aperture(struct agp_softc *sc, uint32_t aperture)
|
||||
{
|
||||
struct agp_amd64_softc *asc = sc->as_chipc;
|
||||
uint32_t apsize;
|
||||
|
||||
apsize = ((aperture - 1) >> 20) ^ 0xff;
|
||||
if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
|
||||
return EINVAL;
|
||||
pci_conf_write(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE,
|
||||
(pci_conf_read(sc->as_pc, asc->ctrl_tag, AGP3_VIA_APSIZE) & ~0xff) |
|
||||
apsize);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: agpreg.h,v 1.12 2007/06/20 08:17:12 sborrill Exp $ */
|
||||
/* $NetBSD: agpreg.h,v 1.13 2007/08/04 09:33:05 kiyohara Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 Doug Rabson
|
||||
@ -231,4 +231,38 @@
|
||||
#define AGP_I915_MSAC 0x62
|
||||
#define AGP_I915_MSAC_APER_128M 0x02
|
||||
|
||||
/*
|
||||
* AMD64 GART registers
|
||||
*/
|
||||
#define AGP_AMD64_APCTRL 0x90
|
||||
#define AGP_AMD64_APBASE 0x94
|
||||
#define AGP_AMD64_ATTBASE 0x98
|
||||
#define AGP_AMD64_CACHECTRL 0x9c
|
||||
#define AGP_AMD64_APCTRL_GARTEN 0x00000001
|
||||
#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
|
||||
#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
|
||||
#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
|
||||
#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
|
||||
#define AGP_AMD64_APBASE_MASK 0x00007fff
|
||||
#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
|
||||
#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
|
||||
#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
|
||||
|
||||
/*
|
||||
* NVIDIA nForce3 registers
|
||||
*/
|
||||
#define AGP_AMD64_NVIDIA_0_APBASE 0x10
|
||||
#define AGP_AMD64_NVIDIA_1_APBASE1 0x50
|
||||
#define AGP_AMD64_NVIDIA_1_APLIMIT1 0x54
|
||||
#define AGP_AMD64_NVIDIA_1_APSIZE 0xa8
|
||||
#define AGP_AMD64_NVIDIA_1_APBASE2 0xd8
|
||||
#define AGP_AMD64_NVIDIA_1_APLIMIT2 0xdc
|
||||
|
||||
/*
|
||||
* ULi M1689 registers
|
||||
*/
|
||||
#define AGP_AMD64_ULI_APBASE 0x10
|
||||
#define AGP_AMD64_ULI_HTT_FEATURE 0x50
|
||||
#define AGP_AMD64_ULI_ENU_SCR 0x54
|
||||
|
||||
#endif /* !_PCI_AGPREG_H_ */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: agpvar.h,v 1.14 2007/03/06 01:09:42 xtraeme Exp $ */
|
||||
/* $NetBSD: agpvar.h,v 1.15 2007/08/04 09:33:05 kiyohara Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 2000 Doug Rabson
|
||||
@ -181,6 +181,7 @@ int agp_generic_unbind_memory(struct agp_softc *, struct agp_memory *);
|
||||
|
||||
/* The vendor has already been matched when these functions are called */
|
||||
int agp_amd_match(const struct pci_attach_args *);
|
||||
int agp_amd64_match(const struct pci_attach_args *);
|
||||
|
||||
int agp_ali_attach(struct device *, struct device *, void *);
|
||||
int agp_amd_attach(struct device *, struct device *, void *);
|
||||
@ -188,6 +189,7 @@ int agp_i810_attach(struct device *, struct device *, void *);
|
||||
int agp_intel_attach(struct device *, struct device *, void *);
|
||||
int agp_via_attach(struct device *, struct device *, void *);
|
||||
int agp_sis_attach(struct device *, struct device *, void *);
|
||||
int agp_amd64_attach(struct device *, struct device *, void *);
|
||||
|
||||
int agp_alloc_dmamem(bus_dma_tag_t, size_t, int, bus_dmamap_t *, void **,
|
||||
bus_addr_t *, bus_dma_segment_t *, int, int *);
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
$NetBSD: pcidevs,v 1.885 2007/07/07 20:30:47 jklos Exp $
|
||||
$NetBSD: pcidevs,v 1.886 2007/08/04 09:33:05 kiyohara Exp $
|
||||
|
||||
/*
|
||||
* Copyright (c) 1995, 1996 Christopher G. Demetriou
|
||||
@ -760,6 +760,7 @@ product ALI M1533 0x1533 M1533 PCI-ISA Bridge
|
||||
product ALI M1541 0x1541 M1541 Host-PCI Bridge
|
||||
product ALI M1543 0x1533 M1543 PCI-ISA Bridge
|
||||
product ALI M1563 0x1563 M1563 PCI-ISA Bridge
|
||||
product ALI M1689 0x1689 M1689 Host-PCI Bridge
|
||||
product ALI M3309 0x3309 M3309 MPEG Decoder
|
||||
product ALI M4803 0x5215 M4803
|
||||
product ALI M5257 0x5257 M5257 PCI Software Modem
|
||||
@ -2772,8 +2773,9 @@ product NVIDIA NFORCE2_400_MCPT_AC 0x008a nForce2 Ultra 400 AC-97
|
||||
product NVIDIA NFORCE2_400_PPB 0x008b nForce2 Ultra 400 PCI-PCI bridge
|
||||
product NVIDIA NFORCE2_400_LAN2 0x008c nForce2 Ultra 400 Ethernet
|
||||
product NVIDIA NFORCE2_400_SATA 0x008e nForce2 Ultra 400 Serial ATA Controller
|
||||
product NVIDIA NFORCE3_PCHB 0x00d1 nForce3 Host-PCI bridge
|
||||
product NVIDIA NFORCE3_PCIB 0x00d0 nForce3 PCI-ISA bridge
|
||||
product NVIDIA NFORCE3_PCHB 0x00d1 nForce3 Host-PCI bridge
|
||||
product NVIDIA NFORCE3_PPB2 0x00d2 nForce3 PCI-PCI
|
||||
product NVIDIA NFORCE3_SMBUS 0x00d4 nForce3 SMBus controller
|
||||
product NVIDIA NFORCE3_ATA133 0x00d5 nForce3 ATA133 IDE
|
||||
product NVIDIA NFORCE3_LAN1 0x00d6 nForce3 Ethernet
|
||||
@ -3578,7 +3580,10 @@ product V3 V96DPC 0xc960 V96DPC i960 (Dual) Host-PCI Bridge
|
||||
|
||||
/* VIA Technologies products, from http://www.via.com.tw/ */
|
||||
product VIATECH VT6305 0x0130 VT6305 IEEE 1394 Host Controller
|
||||
product VIATECH K8M800_0 0x0204 K8M800 Host
|
||||
product VIATECH K8T890_0 0x0238 K8T890 Host
|
||||
product VIATECH KT880 0x0269 KT880 CPU to PCI Bridge
|
||||
product VIATECH K8HTB_0 0x0282 K8HTB Host
|
||||
product VIATECH VT8363_HB 0x0305 VT8363 (Apollo KT133) Host Bridge
|
||||
product VIATECH VT8371_HB 0x0391 VT8371 (Apollo KX133) Host Bridge
|
||||
product VIATECH VT8501_MVP4 0x0501 VT8501 (Apollo MVP4) Host Bridge
|
||||
@ -3624,6 +3629,7 @@ product VIATECH VT8623_VGA 0x3122 VT8623 (Apollo CLE266) VGA Controller
|
||||
product VIATECH VT8623 0x3123 VT8623 (Apollo CLE266) CPU-PCI Bridge
|
||||
product VIATECH VT8233A 0x3147 VT8233A PCI-ISA Bridge
|
||||
product VIATECH VT8237_SATA 0x3149 VT8237 Integrated SATA Controller
|
||||
product VIATECH K8HTB 0x3188 K8HTB Host
|
||||
product VIATECH VT3314_IG 0x3344 VT3314 CN900 UniChrome Integrated Graphics
|
||||
product VIATECH VT8237R_SATA 0x3349 VT8237R Integrated SATA Controller
|
||||
product VIATECH VT6421_RAID 0x3249 VT6421 Serial RAID Controller
|
||||
@ -3649,6 +3655,7 @@ product VIATECH VT8605AGP 0x8605 VT8605 (Apollo ProMedia 133) Host-AGP Bridge
|
||||
product VIATECH VT8633AGP 0xb091 VT8633 (Apollo Pro 266) CPU-AGP Bridge
|
||||
product VIATECH VT8366AGP 0xb099 VT8366 (Apollo KT266) CPU-AGP Bridge
|
||||
product VIATECH VT8377AGP 0xb168 VT8377 CPU-AGP Bridge
|
||||
product VIATECH K8HTB_AGP 0xb188 K8HTB AGP
|
||||
product VIATECH VT8377CEAGP 0xb198 VT8377CE CPU-AGP Bridge
|
||||
|
||||
/* Vortex Computer Systems products */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user