Take a step toward sharing compiled code between sip(4) and gsip(4):
get rid of SIP_DECL() and reduce #ifdef DP83820 code. Next step is to move a bunch of shared code to a new file (if_sipcom.c, say) and compile it *once*. While I am here, add suspend/resume handling to sip(4) and to gsip(4). Tested with the NatSemi sip(4) on the Soekris net4521. I don't have any gsip(4) to test with, and it seems that the few holders of gsip(4) in the world keep them in their attic, anyway.
This commit is contained in:
dyoung
parent
417afa7caa
commit
0c96975093
1562
sys/dev/pci/if_sip.c
1562
sys/dev/pci/if_sip.c
File diff suppressed because it is too large
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@ -1,4 +1,4 @@
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/* $NetBSD: if_sipreg.h,v 1.15 2005/12/11 12:22:49 christos Exp $ */
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/* $NetBSD: if_sipreg.h,v 1.16 2007/12/14 01:55:35 dyoung Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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@ -101,16 +101,15 @@
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* must be aligned to 4-byte (8-byte on DP83820) boundaries.
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*/
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struct sip_desc {
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#ifdef DP83820
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u_int32_t sipd_link; /* link to next descriptor */
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#ifdef DP83820
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u_int32_t sipd_bufptr; /* pointer to DMA segment */
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u_int32_t sipd_cmdsts; /* command/status word */
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u_int32_t sipd_extsts; /* extended status */
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#else
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u_int32_t sipd_link; /* link to next descriptor */
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u_int32_t sipd_cmdsts; /* command/status word */
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u_int32_t sipd_bufptr; /* pointer to DMA segment */
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#endif /* DP83820 */
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u_int32_t sipd_extsts; /* extended status */
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};
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/*
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@ -166,7 +165,6 @@ struct sip_desc {
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#define CMDSTS_Rx_DEST_MUL 0x01000000 /* multicast address */
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#define CMDSTS_Rx_DEST_BRD 0x01800000 /* broadcast address */
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#ifdef DP83820
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/*
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* EXTSTS bits.
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*/
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@ -178,7 +176,6 @@ struct sip_desc {
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#define EXTSTS_IPPKT 0x00020000 /* perform IP header checksum */
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#define EXTSTS_VPKT 0x00010000 /* insert VLAN tag */
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#define EXTSTS_VTCI 0x0000ffff /* VLAN tag control information */
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#endif /* DP83820 */
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/*
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* PCI Configuration space registers.
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@ -223,9 +220,9 @@ struct sip_desc {
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#define SIP_CFG 0x04 /* configuration register */
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#define CFG_LNKSTS 0x80000000 /* link status (83815) */
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#ifdef DP83820
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/* #ifdef DP83820 */
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#define CFG_SPEED1000 0x40000000 /* 1000Mb/s input pin */
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#define CFG_SPEED100 0x20000000 /* 100Mb/s input pin */
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#define CFG83820_SPEED100 0x20000000 /* 100Mb/s input pin */
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#define CFG_DUPSTS 0x10000000 /* full-duplex status */
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#define CFG_TBI_EN 0x01000000 /* ten-bit interface enable */
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#define CFG_MODE_1000 0x00400000 /* 1000Mb/s mode enable */
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@ -239,8 +236,8 @@ struct sip_desc {
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#define CFG_PCI64_DET 0x00002000 /* 64-bit PCI bus detected */
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#define CFG_DATA64_EN 0x00001000 /* 64-bit data enable */
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#define CFG_M64ADDR 0x00000800 /* master 64-bit addressing enable */
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#else
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#define CFG_SPEED100 0x40000000 /* 100Mb/s (83815) */
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/* #else */
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#define CFG83815_SPEED100 0x40000000 /* 100Mb/s (83815) */
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#define CFG_FDUP 0x20000000 /* full duplex (83815) */
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#define CFG_POL 0x10000000 /* 10Mb/s polarity (83815) */
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#define CFG_ANEG_DN 0x08000000 /* autonegotiation done (83815) */
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@ -248,14 +245,14 @@ struct sip_desc {
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#define CFG_PINT_ACEN 0x00020000 /* PHY interrupt auto clear (83815) */
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#define CFG_PAUSE_ADV 0x00010000 /* pause advertise (83815) */
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#define CFG_ANEG_SEL 0x0000e000 /* autonegotiation select (83815) */
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#endif /* DP83820 */
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/* #endif DP83820 */
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#define CFG_PHY_RST 0x00000400 /* PHY reset (83815) */
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#define CFG_PHY_DIS 0x00000200 /* PHY disable (83815) */
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#ifdef DP83820
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/* #ifdef DP83820 */
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#define CFG_EXTSTS_EN 0x00000100 /* extended status enable */
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#else
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/* #else */
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#define CFG_EUPHCOMP 0x00000100 /* 83810 descriptor compat (83815) */
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#endif /* DP83820 */
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/* #endif DP83820 */
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#define CFG_EDBMASTEN 0x00002000 /* 635,900B ?? from linux driver */
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#define CFG_RNDCNT 0x00000400 /* 635,900B ?? from linux driver */
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#define CFG_FAIRBO 0x00000200 /* 635,900B ?? from linux driver */
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@ -264,18 +261,16 @@ struct sip_desc {
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#define CFG_POW 0x00000020 /* program out of window timer */
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#define CFG_EXD 0x00000010 /* excessive defferal timer disable */
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#define CFG_PESEL 0x00000008 /* parity error detection action */
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#ifdef DP83820
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/* #ifdef DP83820 */
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#define CFG_BROM_DIS 0x00000004 /* boot ROM disable */
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#define CFG_EXT_125 0x00000002 /* external 125MHz reference select */
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#endif /* DP83820 */
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/* #endif DP83820 */
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#define CFG_BEM 0x00000001 /* big-endian mode */
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#define SIP_EROMAR 0x08 /* EEPROM access register */
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#ifndef DP83820
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#define EROMAR_REQ 0x00000400 /* SiS 96x specific */
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#define EROMAR_DONE 0x00000200 /* SiS 96x specific */
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#define EROMAR_GNT 0x00000100 /* SiS 96x specific */
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#endif /* DP83820 */
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#define EROMAR_MDC 0x00000040 /* MII clock */
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#define EROMAR_MDDIR 0x00000020 /* MII direction (1 == MAC->PHY) */
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#define EROMAR_MDIO 0x00000010 /* MII data */
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@ -285,7 +280,6 @@ struct sip_desc {
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#define EROMAR_EEDI 0x00000001 /* data in */
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#define SIP_PTSCR 0x0c /* PCI test control register */
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#ifdef DP83820
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#define PTSCR_RBIST_RST 0x00002000 /* SRAM BIST reset */
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#define PTSCR_RBIST_EN 0x00000400 /* SRAM BIST enable */
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#define PTSCR_RBIST_DONE 0x00000200 /* SRAM BIST done */
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@ -297,7 +291,6 @@ struct sip_desc {
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#define PTSCR_EELOAD_EN 0x00000004 /* EEPROM load initiate */
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#define PTSCR_EEBIST_EN 0x00000002 /* EEPROM BIST enable */
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#define PTSCR_EEBIST_FAIL 0x00000001 /* EEPROM BIST failed */
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#else
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#define PTSCR_DIS_TEST 0x40000000 /* discard timer test mode */
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#define PTSCR_EROM_TACC 0x0f000000 /* boot rom access time */
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#define PTSCR_TRRAMADR 0x001ff000 /* TX/RX RAM address */
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@ -306,7 +299,6 @@ struct sip_desc {
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#define PTSCR_TRTMEN 0x00000040 /* transmit RAM test mode enable */
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#define PTSCR_SRTMEN 0x00000020 /* status RAM test mode enable */
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#define PTSCR_SRAMADR 0x0000001f /* status RAM address */
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#endif /* DP83820 */
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#define SIP_ISR 0x10 /* interrupt status register */
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#ifdef DP83820
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@ -326,8 +318,6 @@ struct sip_desc {
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#define ISR_RTABT 0x00020000 /* received target abort */
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#else
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#define ISR_WAKEEVT 0x10000000 /* wake up event */
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#define ISR_PAUSE_END 0x08000000 /* end of transmission pause */
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#define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */
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#define ISR_TXRCMP 0x02000000 /* transmit reset complete */
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#define ISR_RXRCMP 0x01000000 /* receive reset complete */
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#define ISR_DPERR 0x00800000 /* detected parity error */
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@ -335,6 +325,11 @@ struct sip_desc {
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#define ISR_RMABT 0x00200000 /* received master abort */
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#define ISR_RTABT 0x00100000 /* received target abort */
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#endif /* DP83820 */
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/* SiS 900 only */
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#define ISR_PAUSE_END 0x08000000 /* end of transmission pause */
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#define ISR_PAUSE_ST 0x04000000 /* start of transmission pause */
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#define ISR_RXSOVR 0x00010000 /* Rx status FIFO overrun */
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#define ISR_HIBERR 0x00008000 /* high bits error set */
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#ifdef DP83820
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@ -363,11 +358,11 @@ struct sip_desc {
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#define SIP_IER 0x18 /* interrupt enable register */
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#define IER_IE 0x00000001 /* master interrupt enable */
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#ifdef DP83820
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/* #ifdef DP83820 */
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#define SIP_IHR 0x1c /* interrupt hold-off register */
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#define IHR_IHCTL 0x00000100 /* interrupt hold-off control */
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#define IHR_IH 0x000000ff /* interrupt hold-off timer (100us) */
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#else
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/* #else */
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#define SIP_ENPHY 0x1c /* enhanced PHY access register */
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#define ENPHY_PHYDATA 0xffff0000 /* PHY data */
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#define ENPHY_DATA_SHIFT 16
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@ -377,7 +372,7 @@ struct sip_desc {
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#define ENPHY_REGADDR_SHIFT 6
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#define ENPHY_RWCMD 0x00000020 /* 1 == read, 0 == write */
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#define ENPHY_ACCESS 0x00000010 /* PHY access enable */
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#endif /* DP83820 */
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/* #endif DP83820 */
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#define SIP_TXDP 0x20 /* transmit descriptor pointer reg */
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@ -424,7 +419,6 @@ struct sip_desc {
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#define TXCFG_DRTH 0x0000003f /* Tx drain threshold */
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#endif /* DP83820 */
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#ifdef DP83820
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#define SIP_GPIOR 0x2c /* general purpose i/o register */
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#define GPIOR_GP5_IN 0x00004000 /* GP 5 in */
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#define GPIOR_GP4_IN 0x00002000 /* GP 4 in */
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@ -441,7 +435,6 @@ struct sip_desc {
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#define GPIOR_GP3_OUT 0x00000004 /* GP 3 out */
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#define GPIOR_GP2_OUT 0x00000002 /* GP 2 out */
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#define GPIOR_GP1_OUT 0x00000001 /* GP 1 out */
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#endif /* DP83820 */
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#define SIP_RXDP 0x30 /* receive descriptor pointer reg */
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@ -494,16 +487,18 @@ struct sip_desc {
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#define PQCR_TXFAIR 0x00000002 /* Tx fairness enable */
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#define PQCR_TXPQEN 0x00000001 /* Tx priority queueing enable */
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#else
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#define SIP_FLOWCTL 0x38 /* flow control register */
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#define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */
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#define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */
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#define SIP_NS_CCSR 0x3c /* CLKRUN control/status register (83815) */
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#define SIP83815_NS_CCSR 0x3c /* CLKRUN control/status register (83815) */
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#define CCSR_PMESTS 0x00008000 /* PME status */
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#define CCSR_PMEEN 0x00000100 /* PME enable */
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#define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */
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#endif /* DP83820 */
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/* SiS 900 only */
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#define SIP_FLOWCTL 0x38 /* flow control register */
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#define FLOWCTL_PAUSE 0x00000002 /* PAUSE flag */
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#define FLOWCTL_FLOWEN 0x00000001 /* enable flow control */
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#define SIP_NS_WCSR 0x40 /* WoL control/status register (83815/83820) */
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#define SIP_NS_PCR 0x44 /* pause control/status reg (83815/83820) */
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@ -512,7 +507,7 @@ struct sip_desc {
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#define PCR_PS_DA 0x20000000 /* pause on DA */
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#define PCR_PS_ACT 0x10000000 /* pause active */
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#define PCR_PS_RCVD 0x08000000 /* pause packet recieved */
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#ifdef DP83820
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/* #ifdef DP83820 */
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#define PCR_PS_STHI_8 0x03000000 /* Status FIFO Hi Threshold (8packets) */
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#define PCR_PS_STHI_4 0x02000000 /* Status FIFO Hi Threshold (4packets) */
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#define PCR_PS_STHI_2 0x01000000 /* Status FIFO Hi Threshold (2packets) */
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@ -530,10 +525,10 @@ struct sip_desc {
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#define PCR_PS_FFLO_2 0x00040000 /* Data FIFO Lo Threshold (2Kbyte) */
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#define PCR_PS_FFLO_0 0x00000000 /* Data FIFO Lo Threshold (disable) */
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#define PCR_PS_TX 0x00020000 /* Transmit PAUSE frame manually */
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#else
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/* #else */
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#define PCR_PSNEG 0x00200000 /* Pause Negoticated (83815) */
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#define PCR_MLD_EN 0x00010000 /* Manual Load Enable (83815) */
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#endif /* DP83820 */
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/* #endif DP83820 */
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#define PCR_PAUSE_CNT_MASK 0x0000ffff /* pause count mask */
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#define PCR_PAUSE_CNT 65535 /* pause count (512bit-time) */
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@ -632,12 +627,11 @@ struct sip_desc {
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#define MIB_RXTXSQEErrors 0x18
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#endif /* DP83820 */
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#ifndef DP83820
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/* 83815 only */
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#define SIP_NS_PHY(miireg) /* PHY registers (83815) */ \
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(0x80 + ((miireg) << 2))
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#endif
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#ifdef DP83820
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/* #ifdef DP83820 */
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#define SIP_TXDP1 0xa0 /* transmit descriptor pointer (pri 1) */
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#define SIP_TXDP2 0xa4 /* transmit descriptor pointer (pri 2) */
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@ -670,10 +664,12 @@ struct sip_desc {
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#define VDR_VTCI 0xffff0000 /* VLAN tag control information */
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#define VDR_VTYPE 0x0000ffff /* VLAN type field */
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#define SIP_NS_CCSR 0xcc /* CLKRUN control/status register (83815) */
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#define SIP83820_NS_CCSR 0xcc /* CLKRUN control/status register (83820) */
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#if 0
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#define CCSR_PMESTS 0x00008000 /* PME status */
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#define CCSR_PMEEN 0x00000100 /* PME enable */
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#define CCSR_CLKRUN_EN 0x00000001 /* clkrun enable */
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#endif
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#define SIP_TBICR 0xe0 /* TBI control register */
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#define TBICR_MR_LOOPBACK 0x00004000 /* TBI PCS loopback enable */
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@ -703,7 +699,7 @@ struct sip_desc {
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#define SIP_TESR 0xf4 /* TBI extended status register */
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#define TESR_1000FDX 0x00008000 /* we support 1000base FDX */
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#define TESR_1000HDX 0x00004000 /* we support 1000base HDX */
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#else
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/* #else */
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#define SIP_PMCTL 0xb0 /* power management control register */
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#define PMCTL_GATECLK 0x80000000 /* gate dual clock enable */
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#define PMCTL_WAKEALL 0x40000000 /* wake on all Rx OK */
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@ -737,7 +733,7 @@ struct sip_desc {
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#define SIP_WAKEMASK5 0xe4
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#define SIP_WAKEMASK6 0xe8
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#define SIP_WAKEMASK7 0xec
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#endif /* DP83820 */
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/* #endif DP83820 */
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/*
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* Revision codes for the SiS 630 chipset built-in Ethernet.
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