cache, as well. The mini-data cache is 2-way, so src and dst won't
clobber each other, and the smallness of the cache doesn't matter,
since we access each page once sequentially.
While we still have to do the initial clean of the source page, this
saves another 4K of main D$ pollution, and also means we don't have
to do 2 cache passes after the copy is complete (i.e. we can skip the
invalidation of the source page in the main cache, since it's no longer
there).
vs. XScale. Use the mini-data cache for the destination on XScale,
thus saving tossing out 4K of possible-useful data from the main
data cache each time.
This significantly improves every test in lmbench.
and pte_l2_s_cache_mode. The cache-meaningful bits are different
for these descriptor types on some processor models.
* Add pte_*_cache_mask, corresponding to each above, which has a mask
of the cache-meangful bits, and define those for generic and XScale
MMU classes. Note, the L2_S_CACHE_MASK_xscale definition requires
use of the Extended Small Page L2 descriptor (the "X" bit overlaps
with AP bits otherwise).
the data transfer. This is mandatory for data out commands (although none are
used for now), and not forbiddend for data in commands. Also record if we
did transfers any data.
May solve kern/16159 by making the probe more robust in face of fake identify.
L1_C_PROTO_xscale; while they are supposed to be set to 1 on generic
ARM MMUs (according to the SA-110 and ARM920T manuals), they are listed
as "should be zero" in the i80200 manual.
1. Generic (compatible with ARM6)
1. XScale (can be used as generic, but also has certainly nifty extensions).
Define abstract PTE bit defintions for each MMU class. If only one MMU
class is configured into the kernel (based on CPU_* options), then we
get the constants for that MMU class. Otherwise we indirect through
varaibles set up via set_cpufuncs().
XXX The XScale bits are currently the same as the generic bits. Baby steps.
after setting up the prom-based console. If more than one cpu class
is enabled, the wbflush() handler (needed indirectly by com.c) won't
be set up.
- Purge some old pmax mcclock-based code.
- Remove a '#if 1/#endif' pair.
- Use the CPU count register for more accurate microtime (from
sbmips) and delay (based on an evbmips delay function) functions.
- Schedule the next hardclock interrupt more accurately (from
an sgimips patch by Rafal Boni). Clock drift on one board is
now ~7ppm instead of ~330ppm.
- Purge old pmax-based mcclock code.
- Correctly round off some clock-derived variable calculations.
XXX: Some of this code should be migrated to sys/arch/mips.
for the same purpose (ignoring invalid interrupts).
For cards that are not able to stop all interrupts (or we don't know a way
to do that in software, at least) run the clearirq callback even when
ignoring an interrupt because we are not enabled. Otherwise the card would
stop interrupting.
Reserve a driver specific callout handle and an int value in the generic
isic_softc to allow card drivers to implement fancy blinkenlights.
It improves playing/recording quality greatly
and it was almost done by Yosuke Sugahara <penta@fuchu.or.jp>.
Thanks a lot!
Add support of slinear8, slinear16_le, slinear16_be.
do not have ARP configured.
This can be caused by configurations including bridge, ppppoe or vlan but
no ethernet interfaces - which does not make sense. We should add a way
to config(8) to issue this kind of warnings.
pcmcia cards. Now that pcmcia attachements properly handle the activate
callback, this is no longer needed (and is suspect to cause completely
unrelated problems.)
count them when reading the NIC counters - it doubles the count. Read the
NIC counters to prevent counter overflow interrupts, but don't add them to
the interface counters. Don't bother reading the upper counts because they
are just latched when reading the totals.
Fixes final part of PR#11549.
on the following PRO/100 chips:
* i82558 step A4
* i82558 step B0
* i82559 step A0
* i82559S step A
* i82550
* i82550 step C
The interrupt delay is configurable on all microcodable chips. The
maximum "bundle" size (packet count) is configurable on all but the
i82558.
The microcode is enabled by setting IFF_LINK0 on the interface.
Derived from code in FreeBSD.
Significant cleanup, here, including better PTE bit names.
* Add XScale PTE extensions (ECC enable, write-allocate cache mode).
* Mechanical changes everywhere else to update for new pte.h. While
doing this, two bugs (as a result of typos) were fixed in
arm/arm32/bus_dma.c
evbarm/integrator/int_bus_dma.c
the interface was wired to full-duplex mode. Duh.
Also, add OPMODE_TTM to OPMODE_MEDIA_BITS, to insure that it is changed when
we switch between 10 and 100.
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour. Better names for this flag gratefully accepted!
Also adjust comment about known R4000/R4400 revisions.
to be trying to wriggle out of supporting this well. Instead, use
GID_FT to get a list of Port IDs and then use GPN_ID/GNN_ID to find the
port and node wwn. This should make working on fabrics a bit cleaner and
more stable.
This also caused some cleanup of SNS subcommand canonicalization so that
we can actually check for FS_ACC and FS_RJT, and if we get an FS_RJT,
print out the reason and explanation codes.
We'll keep the old GA_NXT method around if people want to uncomment a
controlling definition in ispvar.h.
This also had us clean up ISPASYNC_FABRICDEV to use a local lportdb argument
and to have the caller explicitly say that a device is at the end of the
fabric list.
The ICH on-board Ethernet and some i82559 chips have a bug which
will cause a PCI protocol violation if the chip receives a CU_RESUME
command as it is entering the IDLE state by deasserting #CLKRUN.
(This is the so-called "resume bug" that we previously had an incomplete
work-around for on ICH chipsets.)
The work-around is to disable Dynamic Standby Mode, such that the
chip will never deasert #CLKRUN. Dynamic Standby Mode is disabled
by clearing a bit in the EEPROM and updating the EEPROM (and EEPROM
checksum).
Unfortunately, the chip will only consult the EEPROM setting after
a PCI bus reset, so a system reboot is required once the EEPROM
has been updated (the EEPROM update only needs to happen once,
and the driver usses a warning instructing the user to reboot the
system once the work-around has been applied).
Issue pointed out by David Brownlee, and code more-or-less lifted
from FreeBSD.
the lower bits; UVM provides us page-aligned addresses for
everything. For the paranoid, we'll leave KDASSERT()'s in
that check for this if the kernel is built with DEBUG.
Low-hanging fruit that shaves some cycles.
pmap.h and give them more descriptive names and better comments:
* PT_M -> PVF_MOD (page is modified)
* PT_H -> PVF_REF (page is referenced)
* PT_W -> PVF_WIRED (mapping is wired)
* PT_Wr -> PVF_WRITE (mapping is writable)
* PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)
* Don't refer to VA 0, instead refer to a new variable: vector_page
* Delete the old zero_page_*() functions, replacing them with a new
one: vector_page_setprot().
* When manipulating vector page mappings in user pmaps, only do so if
the vector page is below KERNEL_BASE (if it's above KERNEL_BASE, the
vector page is mapped by the kernel pmap).
* Add a new function, arm32_vector_init(), which takes the virtual
address of the vector page (which MUST be valid when the function
is called) and a bitmask of vectors the kernel is going to take
over, and performs all vector page initialization, including setting
the V bit in the CPU Control register ("relocate vectors to high
address"), if necessary.
when the part being quiried was mapped with a section (!) giving weird
results and had become a mess of goto's.
Complete rewrite and cleaned up the `goto'-jungle entirely ... ripped all
goto's. The resulting code is much better to read and might even have a
small performance gain.
ichiro