Add separate pmap_{zero,copy}_page() functions for generic ARM
vs. XScale. Use the mini-data cache for the destination on XScale, thus saving tossing out 4K of possible-useful data from the main data cache each time. This significantly improves every test in lmbench.
This commit is contained in:
thorpej
parent
338e636672
commit
2092e78cec
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.87 2002/04/09 23:44:01 thorpej Exp $ */
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/* $NetBSD: pmap.c,v 1.88 2002/04/10 00:45:43 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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@ -143,7 +143,7 @@
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#include <machine/param.h>
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#include <arm/arm32/katelib.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.87 2002/04/09 23:44:01 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.88 2002/04/10 00:45:43 thorpej Exp $");
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#ifdef PMAP_DEBUG
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#define PDEBUG(_lev_,_stat_) \
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if (pmap_debug_level >= (_lev_)) \
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@ -1734,8 +1734,9 @@ pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
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* StrongARM accesses to non-cached pages are non-burst making writing
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* _any_ bulk data very slow.
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*/
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#if ARM_MMU_GENERIC == 1
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void
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pmap_zero_page(paddr_t phys)
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pmap_zero_page_generic(paddr_t phys)
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{
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#ifdef DEBUG
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struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
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@ -1757,6 +1758,34 @@ pmap_zero_page(paddr_t phys)
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bzero_page(cdstp);
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cpu_dcache_wbinv_range(cdstp, NBPG);
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}
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#endif /* ARM_MMU_GENERIC == 1 */
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#if ARM_MMU_XSCALE == 1
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void
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pmap_zero_page_xscale(paddr_t phys)
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{
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#ifdef DEBUG
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struct vm_page *pg = PHYS_TO_VM_PAGE(phys);
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if (pg->mdpage.pvh_list != NULL)
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panic("pmap_zero_page: page has mappings");
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#endif
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KDASSERT((phys & PGOFSET) == 0);
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/*
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* Hook in the page, zero it, and purge the cache for that
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* zeroed page. Invalidate the TLB as needed.
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*/
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*cdst_pte = L2_S_PROTO | phys |
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L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
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L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
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cpu_tlb_flushD_SE(cdstp);
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cpu_cpwait();
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bzero_page(cdstp);
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xscale_cache_clean_minidata();
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}
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#endif /* ARM_MMU_XSCALE == 1 */
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/* pmap_pageidlezero()
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*
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@ -1819,8 +1848,9 @@ pmap_pageidlezero(paddr_t phys)
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* hook points. The same comment regarding cachability as in
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* pmap_zero_page also applies here.
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*/
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#if ARM_MMU_GENERIC == 1
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void
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pmap_copy_page(paddr_t src, paddr_t dst)
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pmap_copy_page_generic(paddr_t src, paddr_t dst)
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{
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struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
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#ifdef DEBUG
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@ -1858,6 +1888,50 @@ pmap_copy_page(paddr_t src, paddr_t dst)
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simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */
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cpu_dcache_wbinv_range(cdstp, NBPG);
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}
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#endif /* ARM_MMU_GENERIC == 1 */
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#if ARM_MMU_XSCALE == 1
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void
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pmap_copy_page_xscale(paddr_t src, paddr_t dst)
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{
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struct vm_page *src_pg = PHYS_TO_VM_PAGE(src);
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#ifdef DEBUG
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struct vm_page *dst_pg = PHYS_TO_VM_PAGE(dst);
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if (dst_pg->mdpage.pvh_list != NULL)
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panic("pmap_copy_page: dst page has mappings");
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#endif
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KDASSERT((src & PGOFSET) == 0);
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KDASSERT((dst & PGOFSET) == 0);
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/*
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* Clean the source page. Hold the source page's lock for
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* the duration of the copy so that no other mappings can
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* be created while we have a potentially aliased mapping.
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*/
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simple_lock(&src_pg->mdpage.pvh_slock);
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(void) pmap_clean_page(src_pg->mdpage.pvh_list, TRUE);
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/*
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* Map the pages into the page hook points, copy them, and purge
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* the cache for the appropriate page. Invalidate the TLB
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* as required.
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*/
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*csrc_pte = L2_S_PROTO | src |
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L2_S_PROT(PTE_KERNEL, VM_PROT_READ) | pte_l2_s_cache_mode;
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*cdst_pte = L2_S_PROTO | dst |
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L2_S_PROT(PTE_KERNEL, VM_PROT_WRITE) |
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L2_C | L2_XSCALE_T_TEX(TEX_XSCALE_X); /* mini-data */
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cpu_tlb_flushD_SE(csrcp);
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cpu_tlb_flushD_SE(cdstp);
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cpu_cpwait();
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bcopy_page(csrcp, cdstp);
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cpu_dcache_inv_range(csrcp, NBPG);
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simple_unlock(&src_pg->mdpage.pvh_slock); /* cache is safe again */
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xscale_cache_clean_minidata();
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}
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#endif /* ARM_MMU_XSCALE == 1 */
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#if 0
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void
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@ -3633,6 +3707,9 @@ pt_entry_t pte_l1_s_proto;
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pt_entry_t pte_l1_c_proto;
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pt_entry_t pte_l2_s_proto;
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void (*pmap_copy_page_func)(paddr_t, paddr_t);
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void (*pmap_zero_page_func)(paddr_t);
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#if ARM_MMU_GENERIC == 1
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void
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pmap_pte_init_generic(void)
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@ -3654,6 +3731,9 @@ pmap_pte_init_generic(void)
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pte_l1_s_proto = L1_S_PROTO_generic;
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pte_l1_c_proto = L1_C_PROTO_generic;
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pte_l2_s_proto = L2_S_PROTO_generic;
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pmap_copy_page_func = pmap_copy_page_generic;
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pmap_zero_page_func = pmap_zero_page_generic;
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}
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#if defined(CPU_ARM9)
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@ -3695,6 +3775,9 @@ pmap_pte_init_xscale(void)
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pte_l1_s_proto = L1_S_PROTO_xscale;
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pte_l1_c_proto = L1_C_PROTO_xscale;
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pte_l2_s_proto = L2_S_PROTO_xscale;
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pmap_copy_page_func = pmap_copy_page_xscale;
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pmap_zero_page_func = pmap_zero_page_xscale;
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}
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#if defined(CPU_XSCALE_80200)
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.50 2002/04/09 23:44:02 thorpej Exp $ */
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/* $NetBSD: pmap.h,v 1.51 2002/04/10 00:45:43 thorpej Exp $ */
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/*
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* Copyright (c 2002 Wasabi Systems, Inc.
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@ -271,6 +271,9 @@ extern vaddr_t pmap_curmaxkvaddr;
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defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
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#define ARM_MMU_GENERIC 1
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void pmap_copy_page_generic(paddr_t, paddr_t);
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void pmap_zero_page_generic(paddr_t);
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void pmap_pte_init_generic(void);
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#if defined(CPU_ARM9)
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void pmap_pte_init_arm9(void);
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@ -282,6 +285,9 @@ void pmap_pte_init_arm9(void);
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#if defined(_LKM) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
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#define ARM_MMU_XSCALE 1
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void pmap_copy_page_xscale(paddr_t, paddr_t);
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void pmap_zero_page_xscale(paddr_t);
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void pmap_pte_init_xscale(void);
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#if defined(CPU_XSCALE_80200)
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void pmap_pte_init_i80200(void);
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@ -314,6 +320,9 @@ extern pt_entry_t pte_l1_s_proto;
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extern pt_entry_t pte_l1_c_proto;
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extern pt_entry_t pte_l2_s_proto;
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extern void (*pmap_copy_page_func)(paddr_t, paddr_t);
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extern void (*pmap_zero_page_func)(paddr_t);
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/*****************************************************************************/
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/*
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@ -380,6 +389,9 @@ extern pt_entry_t pte_l2_s_proto;
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#define L1_S_PROTO pte_l1_s_proto
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#define L1_C_PROTO pte_l1_c_proto
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#define L2_S_PROTO pte_l2_s_proto
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#define pmap_copy_page(s, d) (*pmap_copy_page_func)((s), (d))
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#define pmap_zero_page(d) (*pmap_zero_page_func)((d))
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#elif ARM_MMU_GENERIC == 1
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#define L2_S_PROT_U L2_S_PROT_U_generic
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#define L2_S_PROT_W L2_S_PROT_W_generic
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@ -392,6 +404,9 @@ extern pt_entry_t pte_l2_s_proto;
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#define L1_S_PROTO L1_S_PROTO_generic
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#define L1_C_PROTO L1_C_PROTO_generic
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#define L2_S_PROTO L2_S_PROTO_generic
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#define pmap_copy_page(s, d) pmap_copy_page_generic((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_generic((d))
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#elif ARM_MMU_XSCALE == 1
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#define L2_S_PROT_U L2_S_PROT_U_xscale
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#define L2_S_PROT_W L2_S_PROT_W_xscale
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@ -404,6 +419,9 @@ extern pt_entry_t pte_l2_s_proto;
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#define L1_S_PROTO L1_S_PROTO_xscale
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#define L1_C_PROTO L1_C_PROTO_xscale
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#define L2_S_PROTO L2_S_PROTO_xscale
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#define pmap_copy_page(s, d) pmap_copy_page_xscale((s), (d))
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#define pmap_zero_page(d) pmap_zero_page_xscale((d))
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#endif /* ARM_NMMUS > 1 */
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/*
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