Add support for the "CPUSaver" receive interrupt mitigating microcode
on the following PRO/100 chips: * i82558 step A4 * i82558 step B0 * i82559 step A0 * i82559S step A * i82550 * i82550 step C The interrupt delay is configurable on all microcodable chips. The maximum "bundle" size (packet count) is configurable on all but the i82558. The microcode is enabled by setting IFF_LINK0 on the interface. Derived from code in FreeBSD.
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thorpej
parent
0acd189ee0
commit
60e2bbd09a
@ -1,4 +1,4 @@
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/* $NetBSD: i82557.c,v 1.63 2002/04/04 23:15:43 thorpej Exp $ */
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/* $NetBSD: i82557.c,v 1.64 2002/04/05 19:51:04 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc.
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@ -73,7 +73,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.63 2002/04/04 23:15:43 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.64 2002/04/05 19:51:04 thorpej Exp $");
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#include "bpfilter.h"
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#include "rnd.h"
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@ -114,6 +114,8 @@ __KERNEL_RCSID(0, "$NetBSD: i82557.c,v 1.63 2002/04/04 23:15:43 thorpej Exp $");
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#include <dev/ic/i82557reg.h>
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#include <dev/ic/i82557var.h>
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#include <dev/microcode/i8255x/rcvbundl.h>
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/*
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* NOTE! On the Alpha, we have an alignment constraint. The
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* card DMAs the packet immediately following the RFA. However,
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@ -200,12 +202,19 @@ void fxp_eeprom_update_cksum(struct fxp_softc *);
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void fxp_get_info(struct fxp_softc *, u_int8_t *);
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void fxp_tick(void *);
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void fxp_mc_setup(struct fxp_softc *);
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void fxp_load_ucode(struct fxp_softc *);
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void fxp_shutdown(void *);
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void fxp_power(int, void *);
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int fxp_copy_small = 0;
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/*
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* Variables for interrupt mitigating microcode.
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*/
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int fxp_int_delay = 1000; /* usec */
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int fxp_bundle_max = 6; /* packets */
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struct fxp_phytype {
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int fp_phy; /* type of PHY, -1 for MII at the end. */
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void (*fp_init)(struct fxp_softc *);
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@ -1386,10 +1395,12 @@ fxp_stop(struct ifnet *ifp, int disable)
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}
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/*
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* Issue software reset
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* Issue software reset. This unloads any microcode that
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* might already be loaded.
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*/
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CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SELECTIVE_RESET);
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DELAY(10);
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sc->sc_flags &= ~FXPF_UCODE_LOADED;
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CSR_WRITE_4(sc, FXP_CSR_PORT, FXP_PORT_SOFTWARE_RESET);
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DELAY(50);
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/*
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* Release any xmit buffers.
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@ -1506,6 +1517,11 @@ fxp_init(struct ifnet *ifp)
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cbp = &sc->sc_control_data->fcd_configcb;
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memset(cbp, 0, sizeof(struct fxp_cb_config));
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/*
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* Load microcode for this controller.
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*/
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fxp_load_ucode(sc);
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/*
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* This copy is kind of disgusting, but there are a bunch of must be
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* zero and must be one bits in this structure and this is the easiest
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@ -2038,6 +2054,121 @@ fxp_mc_setup(struct fxp_softc *sc)
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}
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}
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static const uint32_t fxp_ucode_d101a[] = D101_A_RCVBUNDLE_UCODE;
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static const uint32_t fxp_ucode_d101b0[] = D101_B0_RCVBUNDLE_UCODE;
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static const uint32_t fxp_ucode_d101ma[] = D101M_B_RCVBUNDLE_UCODE;
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static const uint32_t fxp_ucode_d101s[] = D101S_RCVBUNDLE_UCODE;
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static const uint32_t fxp_ucode_d102[] = D102_B_RCVBUNDLE_UCODE;
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static const uint32_t fxp_ucode_d102c[] = D102_C_RCVBUNDLE_UCODE;
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#define UCODE(x) x, sizeof(x)
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static const struct ucode {
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uint32_t revision;
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const uint32_t *ucode;
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size_t length;
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uint16_t int_delay_offset;
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uint16_t bundle_max_offset;
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} ucode_table[] = {
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{ FXP_REV_82558_A4, UCODE(fxp_ucode_d101a),
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D101_CPUSAVER_DWORD, 0 },
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{ FXP_REV_82558_B0, UCODE(fxp_ucode_d101b0),
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D101_CPUSAVER_DWORD, 0 },
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{ FXP_REV_82559_A0, UCODE(fxp_ucode_d101ma),
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D101M_CPUSAVER_DWORD, D101M_CPUSAVER_BUNDLE_MAX_DWORD },
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{ FXP_REV_82559S_A, UCODE(fxp_ucode_d101s),
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D101S_CPUSAVER_DWORD, D101S_CPUSAVER_BUNDLE_MAX_DWORD },
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{ FXP_REV_82550, UCODE(fxp_ucode_d102),
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D102_B_CPUSAVER_DWORD, D102_B_CPUSAVER_BUNDLE_MAX_DWORD },
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{ FXP_REV_82550_C, UCODE(fxp_ucode_d102c),
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D102_C_CPUSAVER_DWORD, D102_C_CPUSAVER_BUNDLE_MAX_DWORD },
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{ 0, NULL, 0, 0, 0 }
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};
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void
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fxp_load_ucode(struct fxp_softc *sc)
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{
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const struct ucode *uc;
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struct fxp_cb_ucode *cbp = &sc->sc_control_data->fcd_ucode;
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int count;
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if (sc->sc_flags & FXPF_UCODE_LOADED)
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return;
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/*
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* Only load the uCode if the user has requested that
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* we do so.
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*/
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if ((sc->sc_ethercom.ec_if.if_flags & IFF_LINK0) == 0) {
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sc->sc_int_delay = 0;
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sc->sc_bundle_max = 0;
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return;
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}
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for (uc = ucode_table; uc->ucode != NULL; uc++) {
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if (sc->sc_rev == uc->revision)
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break;
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}
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if (uc->ucode == NULL)
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return;
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/* BIG ENDIAN: no need to swap to store 0 */
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cbp->cb_status = 0;
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cbp->cb_command = htole16(FXP_CB_COMMAND_UCODE | FXP_CB_COMMAND_EL);
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cbp->link_addr = 0xffffffff; /* (no) next command */
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memcpy((void *) cbp->ucode, uc->ucode, uc->length);
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if (uc->int_delay_offset)
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*(uint16_t *) &cbp->ucode[uc->int_delay_offset] =
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htole16(fxp_int_delay + (fxp_int_delay / 2));
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if (uc->bundle_max_offset)
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*(uint16_t *) &cbp->ucode[uc->bundle_max_offset] =
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htole16(fxp_bundle_max);
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FXP_CDUCODESYNC(sc, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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/*
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* Download the uCode to the chip.
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*/
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fxp_scb_wait(sc);
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CSR_WRITE_4(sc, FXP_CSR_SCB_GENERAL, sc->sc_cddma + FXP_CDUCODEOFF);
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fxp_scb_cmd(sc, FXP_SCB_COMMAND_CU_START);
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/* ...and wait for it to complete. */
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count = 10000;
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do {
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FXP_CDUCODESYNC(sc,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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DELAY(2);
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} while ((le16toh(cbp->cb_status) & FXP_CB_STATUS_C) == 0 && --count);
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if (count == 0) {
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sc->sc_int_delay = 0;
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sc->sc_bundle_max = 0;
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printf("%s: timeout loading microcode\n",
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sc->sc_dev.dv_xname);
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return;
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}
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if (sc->sc_int_delay != fxp_int_delay ||
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sc->sc_bundle_max != fxp_bundle_max) {
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sc->sc_int_delay = fxp_int_delay;
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sc->sc_bundle_max = fxp_bundle_max;
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printf("%s: Microcode loaded: int delay: %d usec, "
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"max bundle: %d\n", sc->sc_dev.dv_xname,
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sc->sc_int_delay,
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uc->bundle_max_offset == 0 ? 0 : sc->sc_bundle_max);
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}
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sc->sc_flags |= FXPF_UCODE_LOADED;
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}
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int
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fxp_enable(struct fxp_softc *sc)
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{
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@ -1,4 +1,4 @@
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/* $NetBSD: i82557var.h,v 1.26 2001/06/15 22:16:01 thorpej Exp $ */
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/* $NetBSD: i82557var.h,v 1.27 2002/04/05 19:51:05 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999, 2001 The NetBSD Foundation, Inc.
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@ -126,6 +126,11 @@ struct fxp_control_data {
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*/
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struct fxp_cb_mcs fcd_mcscb;
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/*
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* The microcode setup CB.
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*/
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struct fxp_cb_ucode fcd_ucode;
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/*
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* The NIC statistics.
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*/
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@ -138,6 +143,7 @@ struct fxp_control_data {
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#define FXP_CDCONFIGOFF FXP_CDOFF(fcd_configcb)
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#define FXP_CDIASOFF FXP_CDOFF(fcd_iascb)
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#define FXP_CDMCSOFF FXP_CDOFF(fcd_mcscb)
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#define FXP_CDUCODEOFF FXP_CDOFF(fcd_ucode)
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#define FXP_CDSTATSOFF FXP_CDOFF(fcd_stats)
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/*
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@ -210,6 +216,10 @@ struct fxp_softc {
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#define FXPF_READ_ALIGN 0x0040 /* align read access w/ cacheline */
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#define FXPF_WRITE_ALIGN 0x0080 /* end write on cacheline */
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#define FXPF_EXT_TXCB 0x0100 /* enable extended TxCB */
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#define FXPF_UCODE_LOADED 0x0200 /* microcode is loaded */
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int sc_int_delay; /* interrupt delay */
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int sc_bundle_max; /* max packet bundle */
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int sc_txpending; /* number of TX requests pending */
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int sc_txdirty; /* first dirty TX descriptor */
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@ -260,6 +270,10 @@ struct fxp_softc {
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDMCSOFF, sizeof(struct fxp_cb_mcs), (ops))
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#define FXP_CDUCODESYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDUCODEOFF, sizeof(struct fxp_cb_ucode), (ops))
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#define FXP_CDSTATSSYNC(sc, ops) \
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bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap, \
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FXP_CDSTATSOFF, sizeof(struct fxp_stats), (ops))
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