Aren/NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add a "CPU_MIPS_DOUBLE_COUNT" flag for CPUs where the cp0 count register

Browse Source 
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour.  Better names for this flag gratefully accepted!

Also adjust comment about known R4000/R4400 revisions.
This commit is contained in:
simonb 2002-04-05 01:22:16 +00:00
parent e4affd8cbf
commit 2d7c87ebfb
2 changed files with 26 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
sys/arch/mips/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.61 2002/04/03 03:48:33 simonb Exp $ */
/* $NetBSD: cpu.h,v 1.62 2002/04/05 01:22:16 simonb Exp $ */
/*-
* Copyright (c) 1992, 1993
@ -132,6 +132,7 @@ extern int mips3_pg_cached;
#define CPU_MIPS_HAVE_SPECIAL_CCA 0x0008 /* Defaults to '3' if not set. */
#define CPU_MIPS_CACHED_CCA_MASK 0x0070
#define CPU_MIPS_CACHED_CCA_SHIFT 4
#define CPU_MIPS_DOUBLE_COUNT 0x0080 /* 1 cp0 count == 2 clock cycles */
#define MIPS_NOT_SUPP 0x8000
#ifdef _LKM

40
sys/arch/mips/mips/mips_machdep.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.127 2002/04/03 03:47:53 simonb Exp $ */
/* $NetBSD: mips_machdep.c,v 1.128 2002/04/05 01:22:17 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -120,7 +120,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.127 2002/04/03 03:47:53 simonb Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.128 2002/04/05 01:22:17 simonb Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd.h"
@ -247,20 +247,25 @@ static const struct pridtab cputab[] = {
MIPS_NOT_SUPP, "MIPS R6000 CPU" },
/*
* rev 0x00 and 0x30 are R4000, 0x40 and 0x50 are R4400.
* rev 0x00 and 0x30 are R4000, 0x40, 0x50 and 0x60 are R4400.
* should we allow ranges and use 0x00 - 0x3f for R4000 and
* 0x40 - 0xff for R4400?
*/
{ 0, MIPS_R4000, MIPS_REV_R4000_A, CPU_ARCH_MIPS3, 48,
CPU_MIPS_R4K_MMU, "MIPS R4000 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
"MIPS R4000 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4000_B, CPU_ARCH_MIPS3, 48,
CPU_MIPS_R4K_MMU, "MIPS R4000 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
"MIPS R4000 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4400_A, CPU_ARCH_MIPS3, 48,
CPU_MIPS_R4K_MMU, "MIPS R4400 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
"MIPS R4400 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4400_B, CPU_ARCH_MIPS3, 48,
CPU_MIPS_R4K_MMU, "MIPS R4400 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
"MIPS R4400 CPU" },
{ 0, MIPS_R4000, MIPS_REV_R4400_C, CPU_ARCH_MIPS3, 48,
CPU_MIPS_R4K_MMU, "MIPS R4400 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_DOUBLE_COUNT,
"MIPS R4400 CPU" },
{ 0, MIPS_R3LSI, -1, CPU_ARCH_MIPS1, -1,
MIPS_NOT_SUPP, "LSI Logic R3000 derivative" },
@ -306,7 +311,8 @@ static const struct pridtab cputab[] = {
{ 0, MIPS_R5000, -1, CPU_ARCH_MIPS4, 48,
CPU_MIPS_R4K_MMU, "MIPS R5000 CPU" },
{ 0, MIPS_RM5200, -1, CPU_ARCH_MIPS4, 48,
CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV, "QED RM5200 CPU" },
CPU_MIPS_R4K_MMU | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT,
"QED RM5200 CPU" },
/* XXX
* The rm7000 rev 2.0 can have 64 tlbs, and has 6 extra interrupts. See
@ -314,7 +320,8 @@ static const struct pridtab cputab[] = {
* for more details.
*/
{ 0, MIPS_RM7000, -1, CPU_ARCH_MIPS4, 48,
MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV, "QED RM7000 CPU" },
MIPS_NOT_SUPP | CPU_MIPS_CAUSE_IV | CPU_MIPS_DOUBLE_COUNT,
"QED RM7000 CPU" },
/*
* IDT RC32300 core is a 32 bit MIPS2 processor with
@ -346,13 +353,13 @@ static const struct pridtab cputab[] = {
#endif
{ MIPS_PRID_CID_MTI, MIPS_4Kc, -1, -1, 0,
MIPS32_FLAGS, "4Kc" },
MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4Kc" },
{ MIPS_PRID_CID_MTI, MIPS_4KEc, -1, -1, 0,
MIPS32_FLAGS, "4KEc" },
MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KEc" },
{ MIPS_PRID_CID_MTI, MIPS_4KSc, -1, -1, 0,
MIPS32_FLAGS, "4KSc" },
MIPS32_FLAGS | CPU_MIPS_DOUBLE_COUNT, "4KSc" },
{ MIPS_PRID_CID_MTI, MIPS_5Kc, -1, -1, 0,
MIPS64_FLAGS, "5Kc" },
MIPS64_FLAGS | CPU_MIPS_DOUBLE_COUNT, "5Kc" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU1000_R1, -1, -1, 0,
MIPS32_FLAGS, "Au1000 (Rev 1)" },
@ -793,8 +800,9 @@ mips_vector_init(void)
/*
* Check cpu-specific flags.
*/
mips_has_r4k_mmu = mycpu->cpu_flags & CPU_MIPS_R4K_MMU;
mips_has_llsc = !(mycpu->cpu_flags & CPU_MIPS_NO_LLSC);
mips_cpu_flags = mycpu->cpu_flags;
mips_has_r4k_mmu = mips_cpu_flags & CPU_MIPS_R4K_MMU;
mips_has_llsc = !(mips_cpu_flags & CPU_MIPS_NO_LLSC);
if (mycpu->cpu_flags & CPU_MIPS_HAVE_SPECIAL_CCA) {
uint32_t cca;