Add bus master DMA support for the Symphony Labs 82C105 PCI IDE
controller. This part is also found in the Winbond 83C553 Southbrige.
This commit is contained in:
thorpej
parent
aa3369abe2
commit
5eb4257b8e
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@ -1,4 +1,4 @@
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/* $NetBSD: pciide.c,v 1.145 2002/03/24 16:58:12 bouyer Exp $ */
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/* $NetBSD: pciide.c,v 1.146 2002/04/03 17:02:21 thorpej Exp $ */
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/*
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@ -77,7 +77,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.145 2002/03/24 16:58:12 bouyer Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pciide.c,v 1.146 2002/04/03 17:02:21 thorpej Exp $");
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#ifndef WDCDEBUG
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#define WDCDEBUG
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@ -119,6 +119,7 @@ int wdcdebug_pciide_mask = 0;
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#include <dev/pci/pciide_opti_reg.h>
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#include <dev/pci/pciide_hpt_reg.h>
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#include <dev/pci/pciide_acard_reg.h>
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#include <dev/pci/pciide_sl82c105_reg.h>
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#include <dev/pci/cy82c693var.h>
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#include "opt_pciide.h"
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@ -207,9 +208,8 @@ void acard_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void acard_setup_channel __P((struct channel_softc*));
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int acard_pci_intr __P((void *));
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#ifdef PCIIDE_WINBOND_ENABLE
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void winbond_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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#endif
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void sl82c105_chip_map __P((struct pciide_softc*, struct pci_attach_args*));
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void sl82c105_setup_channel __P((struct channel_softc*));
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void pciide_channel_dma_setup __P((struct pciide_channel *));
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int pciide_dma_table_setup __P((struct pciide_softc*, int, int));
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@ -531,19 +531,29 @@ const struct pciide_product_desc pciide_serverworks_products[] = {
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};
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#endif
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#ifdef PCIIDE_WINBOND_ENABLE
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const struct pciide_product_desc pciide_winbond_products[] = {
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{ PCI_PRODUCT_WINBOND_W83C553F_1,
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const struct pciide_product_desc pciide_symphony_products[] = {
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{ PCI_PRODUCT_SYMPHONY_82C105,
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0,
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"Winbond W83C553F IDE controller",
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winbond_chip_map,
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"Symphony Labs 82C105 IDE controller",
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sl82c105_chip_map,
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},
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{ 0,
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0,
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NULL,
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}
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};
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const struct pciide_product_desc pciide_winbond_products[] = {
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{ PCI_PRODUCT_WINBOND_W83C553F_1,
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0,
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"Winbond W83C553F IDE controller",
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sl82c105_chip_map,
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},
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{ 0,
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0,
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NULL,
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}
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};
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#endif
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struct pciide_vendor_desc {
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u_int32_t ide_vendor;
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@ -565,9 +575,8 @@ const struct pciide_vendor_desc pciide_vendors[] = {
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#ifdef PCIIDE_SERVERWORKS_ENABLE
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{ PCI_VENDOR_SERVERWORKS, pciide_serverworks_products },
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#endif
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#ifdef PCIIDE_WINBOND_ENABLE
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{ PCI_VENDOR_SYMPHONY, pciide_symphony_products },
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{ PCI_VENDOR_WINBOND, pciide_winbond_products },
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#endif
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{ 0, NULL }
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};
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@ -4236,3 +4245,155 @@ acard_pci_intr(arg)
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}
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return rv;
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}
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static int
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sl82c105_bugchk(struct pci_attach_args *pa)
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{
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND ||
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PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0)
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return (0);
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if (PCI_REVISION(pa->pa_class) <= 0x05)
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return (1);
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return (0);
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}
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void
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sl82c105_chip_map(sc, pa)
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struct pciide_softc *sc;
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struct pci_attach_args *pa;
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{
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struct pciide_channel *cp;
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bus_size_t cmdsize, ctlsize;
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pcireg_t interface, idecr;
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int channel;
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if (pciide_chipen(sc, pa) == 0)
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return;
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printf("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_dev.dv_xname);
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/*
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* Check to see if we're part of the Winbond 83c553 Southbridge.
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* If so, we need to disable DMA on rev. <= 5 of that chip.
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*/
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if (pci_find_device(pa, sl82c105_bugchk)) {
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printf(" but disabled due to 83c553 rev. <= 0x05");
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sc->sc_dma_ok = 0;
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} else
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pciide_mapreg_dma(sc, pa);
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printf("\n");
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sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 |
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WDC_CAPABILITY_MODE;
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sc->sc_wdcdev.PIO_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.DMA_cap = 2;
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}
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sc->sc_wdcdev.set_modes = sl82c105_setup_channel;
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sc->sc_wdcdev.channels = sc->wdc_chanarray;
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sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS;
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idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR);
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interface = PCI_INTERFACE(pa->pa_class);
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for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if ((channel == 0 && (idecr & IDECR_P0EN) == 0) ||
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(channel == 1 && (idecr & IDECR_P1EN) == 0)) {
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printf("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_dev.dv_xname, cp->name);
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continue;
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}
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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pciide_pci_intr);
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if (cp->hw_ok == 0)
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continue;
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pciide_map_compat_intr(pa, cp, channel, interface);
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if (cp->hw_ok == 0)
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continue;
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sl82c105_setup_channel(&cp->wdc_channel);
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}
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}
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void
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sl82c105_setup_channel(chp)
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struct channel_softc *chp;
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{
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struct ata_drive_datas *drvp;
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struct pciide_channel *cp = (struct pciide_channel*)chp;
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struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc;
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int pxdx_reg, drive;
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pcireg_t pxdx;
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/* Set up DMA if needed. */
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pciide_channel_dma_setup(cp);
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for (drive = 0; drive < 2; drive++) {
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pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR
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: SYMPH_P1D0CR) + (drive * 4);
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pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg);
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pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK);
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pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN);
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip. */
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if ((drvp->drive_flags & DRIVE) == 0) {
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pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx);
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continue;
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}
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if (drvp->drive_flags & DRIVE_DMA) {
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/*
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed.
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*/
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if (drvp->PIO_mode >= 3) {
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if ((drvp->DMA_mode + 2) > drvp->PIO_mode)
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drvp->DMA_mode = drvp->PIO_mode - 2;
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if (drvp->DMA_mode < 1) {
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/*
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* Can't mix both PIO and DMA.
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* Disable DMA.
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*/
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drvp->drive_flags &= ~DRIVE_DMA;
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}
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} else {
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/*
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* Can't mix both PIO and DMA. Disable
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* DMA.
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*/
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drvp->drive_flags &= ~DRIVE_DMA;
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}
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}
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if (drvp->drive_flags & DRIVE_DMA) {
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/* Use multi-word DMA. */
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pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on <<
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PxDx_CMD_ON_SHIFT;
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pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off;
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} else {
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pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on <<
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PxDx_CMD_ON_SHIFT;
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pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off;
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}
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/* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */
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/* ...and set the mode for this drive. */
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pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx);
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}
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pciide_print_modes(cp);
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}
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@ -0,0 +1,112 @@
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/* $NetBSD: pciide_sl82c105_reg.h,v 1.1 2002/04/03 17:02:21 thorpej Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the Symphony Labs 82C105 PCI IDE
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* interface. This 82C105 is also found embedded in the Winbond
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* 83C553 Southbridge.
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*/
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/* PCI configuration space registers */
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#define SYMPH_PORT0_P (PCI_MAPREG_START + 0x00) /* port 0 primary */
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#define SYMPH_PORT0_S (PCI_MAPREG_START + 0x04) /* port 0 secondary */
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#define SYMPH_PORT1_P (PCI_MAPREG_START + 0x08) /* port 1 primary */
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#define SYMPH_PORT1_S (PCI_MAPREG_START + 0x0c) /* port 1 secondary */
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#define SYMPH_BMIDER (PCI_MAPREG_START + 0x10) /* bus master regs */
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#define SYMPH_IDECSR 0x40 /* IDE control/status */
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#define SYMPH_P0D0CR 0x44 /* port 0 drive 0 control */
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#define SYMPH_P0D1CR 0x48 /* port 0 drive 1 control */
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#define SYMPH_P1D0CR 0x4c /* port 1 drive 0 control */
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#define SYMPH_P1D1CR 0c50 /* port 1 drive 1 control */
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#define IDECR_IDE_IRQB (1U << 30) /* IDE_IRQB signal */
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#define IDECR_IDE_IRQA (1U << 28) /* IDE_IRQA signal */
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#define IDECR_RA_SHIFT 16 /* read-ahead duration */
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#define IDECR_RA_MASK (0x7ff << IDECR_RA_SHIFT)
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#define IDECR_LEGIRQ (1U << 1) /* legacy IRQ mode */
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#define IDECR_P1F16 (1U << 5) /* port 1 fast 16 */
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#define IDECR_P1EN (1U << 4) /* port 1 enable */
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#define IDECR_P0F16 (1U << 1) /* port 0 fast 16 */
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#define IDECR_P0EN (1U << 0) /* port 0 enable */
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#define PxDx_USR_SHIFT 16 /* user defined bits */
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#define PxDx_USR_MASK (0xff << PxDx_USR_SHIFT)
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#define PxDx_CMD_ON_SHIFT 8 /* CMD ON time */
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#define PxDx_CMD_ON_MASK (0x1f << PxDx_CMD_ON_SHIFT)
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#define PxDx_PWEN (1U << 7) /* posted write enable */
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#define PxDx_RDYEN (1U << 6) /* IOCHRDY enable */
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#define PxDx_RAEN (1U << 5) /* read-ahead enable */
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#define PxDx_CMD_OFF_MASK (0x1f) /* CMD OFF time */
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/*
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* IDE CMD ON and CMD OFF times for a 33MHz PCI bus clock.
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*
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* These come from Table 4-4 of the 83c553 manual.
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*/
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struct symph_cmdtime {
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int cmd_on; /* cmd on time */
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int cmd_off; /* cmd off time */
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};
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static const struct symph_cmdtime symph_pio_times[]
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__attribute__((__unused__)) = {
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/* programmed actual */
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{ 5, 13 }, /* 6, 14 */
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{ 4, 7 }, /* 5, 8 */
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{ 3, 4 }, /* 4, 5 */
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{ 2, 2 }, /* 3, 3 */
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{ 2, 0 }, /* 3, 1 */
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{ 1, 0 }, /* 2, 1 */
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};
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static const struct symph_cmdtime symph_sw_dma_times[]
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__attribute__((__unused__)) = {
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/* programmed actual */
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{ 15, 15 }, /* 16, 16 */
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};
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static const struct symph_cmdtime symph_mw_dma_times[]
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__attribute__((__unused__)) = {
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/* programmed actual */
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{ 7, 7 }, /* 8, 8 */
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{ 2, 1 }, /* 3, 2 */
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{ 2, 0 }, /* 3, 1 */
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{ 1, 0 }, /* 2, 1 */
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};
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