Rename flags that are really part of the pv_entry/mdpage into
pmap.h and give them more descriptive names and better comments: * PT_M -> PVF_MOD (page is modified) * PT_H -> PVF_REF (page is referenced) * PT_W -> PVF_WIRED (mapping is wired) * PT_Wr -> PVF_WRITE (mapping is writable) * PT_NC -> PVF_NC (mapping is non-cacheable; multiple mappings)
This commit is contained in:
thorpej
parent
d024fa98e3
commit
e539ef03aa
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.77 2002/04/04 02:06:46 thorpej Exp $ */
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/* $NetBSD: pmap.c,v 1.78 2002/04/04 04:25:44 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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@ -143,7 +143,7 @@
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#include <machine/param.h>
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#include <arm/arm32/katelib.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.77 2002/04/04 02:06:46 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.78 2002/04/04 04:25:44 thorpej Exp $");
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#ifdef PMAP_DEBUG
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#define PDEBUG(_lev_,_stat_) \
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if (pmap_debug_level >= (_lev_)) \
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@ -815,7 +815,7 @@ pmap_enter_pv(struct vm_page *pg, struct pv_entry *pve, struct pmap *pmap,
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pve->pv_next = pg->mdpage.pvh_list; /* add to ... */
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pg->mdpage.pvh_list = pve; /* ... locked list */
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simple_unlock(&pg->mdpage.pvh_slock); /* unlock, done! */
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if (pve->pv_flags & PT_W)
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if (pve->pv_flags & PVF_WIRED)
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++pmap->pm_stats.wired_count;
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}
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@ -840,7 +840,7 @@ pmap_remove_pv(struct vm_page *pg, struct pmap *pmap, vaddr_t va)
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while (pve) {
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if (pve->pv_pmap == pmap && pve->pv_va == va) { /* match? */
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*prevptr = pve->pv_next; /* remove it! */
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if (pve->pv_flags & PT_W)
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if (pve->pv_flags & PVF_WIRED)
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--pmap->pm_stats.wired_count;
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break;
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}
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@ -879,8 +879,8 @@ pmap_modify_pv(struct pmap *pmap, vaddr_t va, struct vm_page *pg,
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oflags = npv->pv_flags;
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npv->pv_flags = flags =
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((oflags & ~bic_mask) ^ eor_mask);
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if ((flags ^ oflags) & PT_W) {
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if (flags & PT_W)
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if ((flags ^ oflags) & PVF_WIRED) {
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if (flags & PVF_WIRED)
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++pmap->pm_stats.wired_count;
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else
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--pmap->pm_stats.wired_count;
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@ -1695,7 +1695,7 @@ pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
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/* The page is mapped non-cacheable in
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* this map. No need to flush the cache.
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*/
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if (npv->pv_flags & PT_NC) {
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if (npv->pv_flags & PVF_NC) {
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#ifdef DIAGNOSTIC
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if (cache_needs_cleaning)
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panic("pmap_clean_page: "
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@ -1711,7 +1711,7 @@ pmap_clean_page(struct pv_entry *pv, boolean_t is_src)
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/* If the page is not writable and this
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is the source, then there is no need
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to flush it from the cache. */
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else if (is_src && ! (npv->pv_flags & PT_Wr))
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else if (is_src && ! (npv->pv_flags & PVF_WRITE))
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continue;
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#endif
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if (cache_needs_cleaning){
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@ -1974,15 +1974,15 @@ pmap_vac_me_kpmap(struct pmap *pmap, struct vm_page *pg, pt_entry_t *ptes,
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for (pv = pg->mdpage.pvh_list; pv != NULL; pv = pv->pv_next) {
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if (pv->pv_pmap != pmap) {
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user_entries++;
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if (pv->pv_flags & PT_Wr)
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if (pv->pv_flags & PVF_WRITE)
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user_writable++;
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if ((pv->pv_flags & PT_NC) == 0)
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if ((pv->pv_flags & PVF_NC) == 0)
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user_cacheable++;
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} else {
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kernel_entries++;
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if (pv->pv_flags & PT_Wr)
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if (pv->pv_flags & PVF_WRITE)
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kernel_writable++;
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if ((pv->pv_flags & PT_NC) == 0)
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if ((pv->pv_flags & PVF_NC) == 0)
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kernel_cacheable++;
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}
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}
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@ -2017,8 +2017,8 @@ pmap_vac_me_kpmap(struct pmap *pmap, struct vm_page *pg, pt_entry_t *ptes,
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* skip this entry also.
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*/
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if (kernel_entries > 0 &&
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(pv->pv_flags & (PT_NC | PT_Wr)) ==
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(PT_NC | PT_Wr))
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(pv->pv_flags & (PVF_NC | PVF_WRITE)) ==
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(PVF_NC | PVF_WRITE))
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continue;
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/*
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* Similarly if there are no kernel-writable
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@ -2026,7 +2026,7 @@ pmap_vac_me_kpmap(struct pmap *pmap, struct vm_page *pg, pt_entry_t *ptes,
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* read-only/cacheable.
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*/
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if (kernel_writable == 0 &&
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(pv->pv_flags & (PT_NC | PT_Wr)) == 0)
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(pv->pv_flags & (PVF_NC | PVF_WRITE)) == 0)
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continue;
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/*
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* For some of the remaining cases, we know
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@ -2080,15 +2080,15 @@ pmap_vac_me_user(struct pmap *pmap, struct vm_page *pg, pt_entry_t *ptes,
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if (entries++ == 0)
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pv = npv;
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/* Cacheable mappings */
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if ((npv->pv_flags & PT_NC) == 0) {
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if ((npv->pv_flags & PVF_NC) == 0) {
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cacheable_entries++;
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if (kpmap == npv->pv_pmap)
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kern_cacheable++;
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}
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/* Writable mappings */
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if (npv->pv_flags & PT_Wr)
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if (npv->pv_flags & PVF_WRITE)
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++writable;
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} else if (npv->pv_flags & PT_Wr)
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} else if (npv->pv_flags & PVF_WRITE)
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other_writable = 1;
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}
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@ -2109,9 +2109,9 @@ pmap_vac_me_user(struct pmap *pmap, struct vm_page *pg, pt_entry_t *ptes,
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for (npv = pv; npv; npv = npv->pv_next) {
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if ((pmap == npv->pv_pmap
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|| kpmap == npv->pv_pmap) &&
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(npv->pv_flags & PT_NC) == 0) {
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(npv->pv_flags & PVF_NC) == 0) {
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ptes[arm_btop(npv->pv_va)] &= ~(PT_C | PT_B);
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npv->pv_flags |= PT_NC;
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npv->pv_flags |= PVF_NC;
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/*
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* If this page needs flushing from the
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* cache, and we aren't going to do it
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@ -2141,9 +2141,9 @@ pmap_vac_me_user(struct pmap *pmap, struct vm_page *pg, pt_entry_t *ptes,
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for (npv = pv; npv; npv = npv->pv_next) {
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if ((pmap == npv->pv_pmap ||
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(kpmap == npv->pv_pmap && other_writable == 0)) &&
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(npv->pv_flags & PT_NC)) {
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(npv->pv_flags & PVF_NC)) {
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ptes[arm_btop(npv->pv_va)] |= pte_cache_mode;
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npv->pv_flags &= ~PT_NC;
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npv->pv_flags &= ~PVF_NC;
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}
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}
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}
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@ -2361,7 +2361,7 @@ pmap_remove_all(struct vm_page *pg)
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--pmap->pm_stats.resident_count;
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/* Wired bit */
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if (pv->pv_flags & PT_W)
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if (pv->pv_flags & PVF_WIRED)
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--pmap->pm_stats.wired_count;
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/*
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@ -2472,7 +2472,7 @@ pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
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/* Clear write flag */
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if ((pg = PHYS_TO_VM_PAGE(pa)) != NULL) {
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simple_lock(&pg->mdpage.pvh_slock);
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(void) pmap_modify_pv(pmap, sva, pg, PT_Wr, 0);
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(void) pmap_modify_pv(pmap, sva, pg, PVF_WRITE, 0);
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pmap_vac_me_harder(pmap, pg, ptes, FALSE);
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simple_unlock(&pg->mdpage.pvh_slock);
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}
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@ -2565,9 +2565,9 @@ pmap_enter(struct pmap *pmap, vaddr_t va, paddr_t pa, vm_prot_t prot,
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nflags = 0;
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if (prot & VM_PROT_WRITE)
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nflags |= PT_Wr;
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nflags |= PVF_WRITE;
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if (wired)
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nflags |= PT_W;
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nflags |= PVF_WIRED;
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/* Is the pte valid ? If so then this page is already mapped */
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if (l2pte_valid(opte)) {
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@ -2580,7 +2580,7 @@ pmap_enter(struct pmap *pmap, vaddr_t va, paddr_t pa, vm_prot_t prot,
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if (pg != NULL) {
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simple_lock(&pg->mdpage.pvh_slock);
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(void) pmap_modify_pv(pmap, va, pg,
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PT_Wr | PT_W, nflags);
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PVF_WRITE | PVF_WIRED, nflags);
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simple_unlock(&pg->mdpage.pvh_slock);
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}
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} else {
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@ -2650,10 +2650,10 @@ pmap_enter(struct pmap *pmap, vaddr_t va, paddr_t pa, vm_prot_t prot,
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npte |= pte_cache_mode;
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if (flags & VM_PROT_WRITE) {
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npte |= L2_SPAGE | PT_AP(AP_W);
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pg->mdpage.pvh_attrs |= PT_H | PT_M;
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pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD;
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} else if (flags & VM_PROT_ALL) {
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npte |= L2_SPAGE;
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pg->mdpage.pvh_attrs |= PT_H;
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pg->mdpage.pvh_attrs |= PVF_REF;
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} else
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npte |= L2_INVAL;
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} else {
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@ -2739,7 +2739,7 @@ pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
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case VM_PROT_READ:
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case VM_PROT_READ|VM_PROT_EXECUTE:
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pmap_clearbit(pg, PT_Wr);
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pmap_clearbit(pg, PVF_WRITE);
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break;
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default:
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@ -2780,7 +2780,7 @@ pmap_unwire(struct pmap *pmap, vaddr_t va)
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/* Update the wired bit in the pv entry for this page. */
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simple_lock(&pg->mdpage.pvh_slock);
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(void) pmap_modify_pv(pmap, va, pg, PT_W, 0);
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(void) pmap_modify_pv(pmap, va, pg, PVF_WIRED, 0);
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simple_unlock(&pg->mdpage.pvh_slock);
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}
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#ifdef DIAGNOSTIC
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@ -2984,8 +2984,8 @@ pmap_clearbit(struct vm_page *pg, u_int maskbits)
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pv->pv_flags &= ~maskbits;
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ptes = pmap_map_ptes(pv->pv_pmap); /* locks pmap */
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KASSERT(pmap_pde_v(pmap_pde(pv->pv_pmap, va)));
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if (maskbits & (PT_Wr|PT_M)) {
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if ((pv->pv_flags & PT_NC)) {
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if (maskbits & (PVF_WRITE|PVF_MOD)) {
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if ((pv->pv_flags & PVF_NC)) {
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/*
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* Entry is not cacheable: reenable
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* the cache, nothing to flush
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@ -3002,9 +3002,9 @@ pmap_clearbit(struct vm_page *pg, u_int maskbits)
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* permission.
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*
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*/
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if (maskbits & PT_Wr) {
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if (maskbits & PVF_WRITE) {
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ptes[arm_btop(va)] |= pte_cache_mode;
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pv->pv_flags &= ~PT_NC;
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pv->pv_flags &= ~PVF_NC;
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}
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} else if (pmap_is_curpmap(pv->pv_pmap)) {
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/*
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@ -3019,7 +3019,7 @@ pmap_clearbit(struct vm_page *pg, u_int maskbits)
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ptes[arm_btop(va)] &= ~PT_AP(AP_W);
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}
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if (maskbits & PT_H)
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if (maskbits & PVF_REF)
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ptes[arm_btop(va)] =
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(ptes[arm_btop(va)] & ~L2_MASK) | L2_INVAL;
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@ -3050,9 +3050,9 @@ pmap_clear_modify(struct vm_page *pg)
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{
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boolean_t rv;
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if (pg->mdpage.pvh_attrs & PT_M) {
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if (pg->mdpage.pvh_attrs & PVF_MOD) {
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rv = TRUE;
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pmap_clearbit(pg, PT_M);
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pmap_clearbit(pg, PVF_MOD);
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} else
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rv = FALSE;
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@ -3072,9 +3072,9 @@ pmap_clear_reference(struct vm_page *pg)
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{
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boolean_t rv;
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if (pg->mdpage.pvh_attrs & PT_H) {
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if (pg->mdpage.pvh_attrs & PVF_REF) {
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rv = TRUE;
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pmap_clearbit(pg, PT_H);
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pmap_clearbit(pg, PVF_REF);
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} else
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rv = FALSE;
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@ -3145,7 +3145,7 @@ pmap_modified_emulation(struct pmap *pmap, vaddr_t va)
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* a write has occurred we can correct this and also set the
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* modified bit
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*/
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if (~flags & PT_Wr) {
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if (~flags & PVF_WRITE) {
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simple_unlock(&pg->mdpage.pvh_slock);
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goto out;
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}
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@ -3153,14 +3153,14 @@ pmap_modified_emulation(struct pmap *pmap, vaddr_t va)
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PDEBUG(0,
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printf("pmap_modified_emulation: Got a hit va=%08lx, pte = %08x\n",
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va, ptes[arm_btop(va)]));
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pg->mdpage.pvh_attrs |= PT_H | PT_M;
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pg->mdpage.pvh_attrs |= PVF_REF | PVF_MOD;
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/*
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* Re-enable write permissions for the page. No need to call
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* pmap_vac_me_harder(), since this is just a
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* modified-emulation fault, and the PT_Wr bit isn't changing. We've
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* already set the cacheable bits based on the assumption that we
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* can write to this page.
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* modified-emulation fault, and the PVF_WRITE bit isn't changing.
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* We've already set the cacheable bits based on the assumption
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* that we can write to this page.
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*/
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ptes[arm_btop(va)] =
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(ptes[arm_btop(va)] & ~L2_MASK) | L2_SPAGE | PT_AP(AP_W);
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@ -3219,7 +3219,7 @@ pmap_handled_emulation(struct pmap *pmap, vaddr_t va)
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PDEBUG(0,
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printf("pmap_handled_emulation: Got a hit va=%08lx pte = %08x\n",
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va, ptes[arm_btop(va)]));
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pg->mdpage.pvh_attrs |= PT_H;
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pg->mdpage.pvh_attrs |= PVF_REF;
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ptes[arm_btop(va)] = (ptes[arm_btop(va)] & ~L2_MASK) | L2_SPAGE;
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PDEBUG(0, printf("->(%08x)\n", ptes[arm_btop(va)]));
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.h,v 1.42 2002/04/03 23:33:31 thorpej Exp $ */
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/* $NetBSD: pmap.h,v 1.43 2002/04/04 04:25:45 thorpej Exp $ */
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/*
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* Copyright (c) 1994,1995 Mark Brinicombe.
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@ -108,6 +108,23 @@ typedef struct pv_addr {
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#define PTE_NOCACHE 0
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#define PTE_CACHE 1
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/*
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* Flags that indicate attributes of pages or mappings of pages.
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*
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* The PVF_MOD and PVF_REF flags are stored in the mdpage for each
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* page. PVF_WIRED, PVF_WRITE, and PVF_NC are kept in individual
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* pv_entry's for each page. They live in the same "namespace" so
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* that we can clear multiple attributes at a time.
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*
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* Note the "non-cacheable" flag generally means the page has
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* multiple mappings in a given address space.
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*/
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#define PVF_MOD 0x01 /* page is modified */
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#define PVF_REF 0x02 /* page is referenced */
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#define PVF_WIRED 0x04 /* mapping is wired */
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#define PVF_WRITE 0x08 /* mapping is writable */
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#define PVF_NC 0x10 /* mapping is non-cacheable */
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/*
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* Commonly referenced structures
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*/
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@ -121,8 +138,10 @@ extern int pmap_debug_level; /* Only exists if PMAP_DEBUG */
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#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
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#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
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#define pmap_is_modified(pg) (((pg)->mdpage.pvh_attrs & PT_M) != 0)
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#define pmap_is_referenced(pg) (((pg)->mdpage.pvh_attrs & PT_H) != 0)
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#define pmap_is_modified(pg) \
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(((pg)->mdpage.pvh_attrs & PVF_MOD) != 0)
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#define pmap_is_referenced(pg) \
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(((pg)->mdpage.pvh_attrs & PVF_REF) != 0)
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#define pmap_copy(dp, sp, da, l, sa) /* nothing */
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@ -1,4 +1,4 @@
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/* $NetBSD: pte.h,v 1.3 2002/04/03 00:46:53 reinoud Exp $ */
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/* $NetBSD: pte.h,v 1.4 2002/04/04 04:25:45 thorpej Exp $ */
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/*
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* Copyright (c) 1994 Mark Brinicombe.
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@ -37,7 +37,6 @@
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#define PDSHIFT 20 /* LOG2(NBPDR) */
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#define NBPD (1 << PDSHIFT) /* bytes/page dir */
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#define NPTEPD (NBPD / NBPG)
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||||
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||||
#ifndef _LOCORE
|
||||
typedef u_int32_t pd_entry_t; /* page directory entry */
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|
@ -80,14 +79,6 @@ extern pt_entry_t pte_cache_mode;
|
|||
#define PT_CACHEABLE (pte_cache_mode)
|
||||
#endif
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||||
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||||
/* Page R/M attributes (in pmseg.attrs). */
|
||||
#define PT_M 0x01 /* Virt - Modified */
|
||||
#define PT_H 0x02 /* Virt - Handled (Used) */
|
||||
/* Mapping wired/writeable/cacheable attributes (in pv_flags). */
|
||||
#define PT_W 0x04 /* Virt - Wired */
|
||||
#define PT_Wr 0x08 /* Virt / Phys Write */
|
||||
#define PT_NC 0x10 /* Cacheing disabled (multi-mapped page) */
|
||||
|
||||
/* access permissions for L2 pages (all sub pages have the same perms) */
|
||||
#define PT_AP(x) ((x << 10) | (x << 8) | (x << 6) | (x << 4))
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue