Define 2 classes of ARM MMUs:
1. Generic (compatible with ARM6) 1. XScale (can be used as generic, but also has certainly nifty extensions). Define abstract PTE bit defintions for each MMU class. If only one MMU class is configured into the kernel (based on CPU_* options), then we get the constants for that MMU class. Otherwise we indirect through varaibles set up via set_cpufuncs(). XXX The XScale bits are currently the same as the generic bits. Baby steps.
This commit is contained in:
thorpej
parent
30453d09bc
commit
c535f4ffc4
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@ -1,4 +1,4 @@
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/* $NetBSD: cpufunc.c,v 1.39 2002/04/05 16:58:03 thorpej Exp $ */
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/* $NetBSD: cpufunc.c,v 1.40 2002/04/09 21:00:42 thorpej Exp $ */
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/*
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* arm7tdmi support code Copyright (c) 2001 John Fremlin
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@ -719,6 +719,7 @@ set_cpufuncs()
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cpufuncs = arm6_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype_table();
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pmap_pte_init_generic();
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return 0;
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}
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#endif /* CPU_ARM6 */
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@ -729,6 +730,7 @@ set_cpufuncs()
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cpufuncs = arm7_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype_table();
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pmap_pte_init_generic();
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return 0;
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}
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#endif /* CPU_ARM7 */
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@ -739,6 +741,7 @@ set_cpufuncs()
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cpufuncs = arm7tdmi_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0;
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get_cachetype_cp15();
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pmap_pte_init_generic();
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return 0;
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}
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#endif
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@ -748,15 +751,16 @@ set_cpufuncs()
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cpufuncs = arm8_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 0; /* XXX correct? */
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get_cachetype_cp15();
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pmap_pte_init_generic();
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return 0;
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}
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#endif /* CPU_ARM8 */
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#ifdef CPU_ARM9
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if (cputype == CPU_ID_ARM920T) {
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pte_cache_mode = L2_C; /* Select write-through cacheing. */
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cpufuncs = arm9_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */
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get_cachetype_cp15();
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pmap_pte_init_arm9();
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return 0;
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}
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#endif /* CPU_ARM9 */
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@ -766,6 +770,7 @@ set_cpufuncs()
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cpufuncs = sa110_cpufuncs;
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cpu_reset_needs_v4_MMU_disable = 1; /* SA needs it */
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get_cachetype_table();
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pmap_pte_init_generic();
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/*
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* Enable the right variant of sleeping.
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*/
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@ -811,7 +816,6 @@ set_cpufuncs()
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:
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: "r" (BCUCTL_E0|BCUCTL_E1|BCUCTL_EV));
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pte_cache_mode = L2_C; /* Select write-through cacheing. */
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cpufuncs = xscale_cpufuncs;
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/*
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@ -826,6 +830,7 @@ set_cpufuncs()
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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get_cachetype_cp15();
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pmap_pte_init_i80200();
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return 0;
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}
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#endif /* CPU_XSCALE_80200 */
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@ -849,6 +854,7 @@ set_cpufuncs()
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cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
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get_cachetype_cp15();
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pmap_pte_init_xscale();
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return 0;
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}
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#endif /* CPU_XSCALE_80321 */
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@ -1,4 +1,4 @@
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/* $NetBSD: pmap.c,v 1.84 2002/04/09 19:44:22 thorpej Exp $ */
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/* $NetBSD: pmap.c,v 1.85 2002/04/09 21:00:43 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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@ -143,7 +143,7 @@
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#include <machine/param.h>
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#include <arm/arm32/katelib.h>
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.84 2002/04/09 19:44:22 thorpej Exp $");
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__KERNEL_RCSID(0, "$NetBSD: pmap.c,v 1.85 2002/04/09 21:00:43 thorpej Exp $");
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#ifdef PMAP_DEBUG
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#define PDEBUG(_lev_,_stat_) \
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if (pmap_debug_level >= (_lev_)) \
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@ -3607,3 +3607,87 @@ pmap_map_chunk(vaddr_t l1pt, vaddr_t va, paddr_t pa, vsize_t size,
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#endif
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return (size);
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}
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/********************** PTE initialization routines **************************/
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/*
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* These routines are called when the CPU type is identified to set up
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* the PTE prototypes, cache modes, etc.
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*
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* The variables are always here, just in case LKMs need to reference
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* them (though, they shouldn't).
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*/
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pt_entry_t pte_cache_mode;
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pt_entry_t pte_cache_mask;
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pt_entry_t pte_l2_s_prot_u;
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pt_entry_t pte_l2_s_prot_w;
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pt_entry_t pte_l2_s_prot_mask;
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pt_entry_t pte_l1_s_proto;
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pt_entry_t pte_l1_c_proto;
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pt_entry_t pte_l2_s_proto;
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#if ARM_MMU_GENERIC == 1
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void
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pmap_pte_init_generic(void)
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{
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pte_cache_mode = L2_B|L2_C;
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pte_cache_mask = L2_CACHE_MASK_generic;
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pte_l2_s_prot_u = L2_S_PROT_U_generic;
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pte_l2_s_prot_w = L2_S_PROT_W_generic;
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pte_l2_s_prot_mask = L2_S_PROT_MASK_generic;
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pte_l1_s_proto = L1_S_PROTO_generic;
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pte_l1_c_proto = L1_C_PROTO_generic;
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pte_l2_s_proto = L2_S_PROTO_generic;
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}
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#if defined(CPU_ARM9)
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void
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pmap_pte_init_arm9(void)
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{
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/*
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* ARM9 is compatible with generic, but we want to use
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* write-through caching for now.
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*/
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pmap_pte_init_generic();
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pte_cache_mode = L2_C;
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}
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#endif /* CPU_ARM9 */
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#endif /* ARM_MMU_GENERIC == 1 */
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#if ARM_MMU_XSCALE == 1
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void
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pmap_pte_init_xscale(void)
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{
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pte_cache_mode = L2_B|L2_C;
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pte_cache_mask = L2_CACHE_MASK_xscale;
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pte_l2_s_prot_u = L2_S_PROT_U_xscale;
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pte_l2_s_prot_w = L2_S_PROT_W_xscale;
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pte_l2_s_prot_mask = L2_S_PROT_MASK_xscale;
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pte_l1_s_proto = L1_S_PROTO_xscale;
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pte_l1_c_proto = L1_C_PROTO_xscale;
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pte_l2_s_proto = L2_S_PROTO_xscale;
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}
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#if defined(CPU_XSCALE_80200)
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void
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pmap_pte_init_i80200(void)
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{
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/*
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* Use write-through caching on the i80200.
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*/
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pmap_pte_init_xscale();
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pte_cache_mode = L2_C;
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}
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#endif /* CPU_XSCALE_80200 */
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#endif /* ARM_MMU_XSCALE == 1 */
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@ -1,4 +1,39 @@
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/* $NetBSD: pmap.h,v 1.45 2002/04/09 19:37:17 thorpej Exp $ */
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/* $NetBSD: pmap.h,v 1.46 2002/04/09 21:00:44 thorpej Exp $ */
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/*
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* Copyright (c 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1994,1995 Mark Brinicombe.
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@ -219,6 +254,60 @@ extern vaddr_t pmap_curmaxkvaddr;
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#define KERNEL_PD_SIZE \
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(L1_TABLE_SIZE - (KERNEL_BASE >> L1_S_SHIFT) * sizeof(pd_entry_t))
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/************************* ARM MMU configuration *****************************/
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/*
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* We define several classes of ARM MMU, here:
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*
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* ARM_MMU_GENERIC Generic ARM MMU, compatible with ARM6.
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*
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* ARM_MMU_XSCALE XScale MMU. Compatible with generic ARM
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* MMU, but also has several extensions which
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* require different PTE layout to use.
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*/
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#if defined(_LKM) || defined(CPU_ARM6) || defined(CPU_ARM7) || \
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defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
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defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
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#define ARM_MMU_GENERIC 1
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void pmap_pte_init_generic(void);
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#if defined(CPU_ARM9)
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void pmap_pte_init_arm9(void);
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#endif /* CPU_ARM9 */
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#else
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#define ARM_MMU_GENERIC 0
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#endif
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#if defined(_LKM) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321)
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#define ARM_MMU_XSCALE 1
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void pmap_pte_init_xscale(void);
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#if defined(CPU_XSCALE_80200)
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void pmap_pte_init_i80200(void);
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#endif /* CPU_XSCALE_80200 */
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#else
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#define ARM_MMU_XSCALE 0
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#endif
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#define ARM_NMMUS (ARM_MMU_GENERIC + ARM_MMU_XSCALE)
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#if ARM_NMMUS == 0
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#error ARM_NMMUS is 0
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#endif
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extern pt_entry_t pte_cache_mode;
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extern pt_entry_t pte_cache_mask;
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extern pt_entry_t pte_l2_s_prot_u;
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extern pt_entry_t pte_l2_s_prot_w;
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extern pt_entry_t pte_l2_s_prot_mask;
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extern pt_entry_t pte_l1_s_proto;
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extern pt_entry_t pte_l1_c_proto;
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extern pt_entry_t pte_l2_s_proto;
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/*****************************************************************************/
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/*
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* tell MI code that the cache is virtually-indexed *and* virtually-tagged.
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*/
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#define L2_L_PROT_W (L2_AP(AP_W))
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#define L2_L_PROT_MASK (L2_L_PROT_U|L2_L_PROT_W)
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#define L2_S_PROT_U (L2_AP(AP_U))
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#define L2_S_PROT_W (L2_AP(AP_W))
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#define L2_S_PROT_MASK (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_S_PROT_U_generic (L2_AP(AP_U))
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#define L2_S_PROT_W_generic (L2_AP(AP_W))
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#define L2_S_PROT_MASK_generic (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_CACHE_MASK (L2_B|L2_C)
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#define L2_S_PROT_U_xscale (L2_AP(AP_U))
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#define L2_S_PROT_W_xscale (L2_AP(AP_W))
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#define L2_S_PROT_MASK_xscale (L2_S_PROT_U|L2_S_PROT_W)
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#define L2_CACHE_MASK_generic (L2_B|L2_C)
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#define L2_CACHE_MASK_xscale (L2_B|L2_C)
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#define L1_S_PROTO_generic (L1_TYPE_S | L1_S_IMP)
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#define L1_S_PROTO_xscale (L1_TYPE_S | L1_S_IMP) /* XXX IMP */
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#define L1_C_PROTO_generic (L1_TYPE_C | L1_C_IMP2)
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#define L1_C_PROTO_xscale (L1_TYPE_C | L1_C_IMP2) /* XXX IMP */
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#define L2_L_PROTO (L2_TYPE_L)
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#define L2_S_PROTO_generic (L2_TYPE_S)
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#define L2_S_PROTO_xscale (L2_TYPE_S)
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/*
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* User-visible names for the ones that vary with MMU class.
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*/
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#if ARM_NMMUS > 1
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/* More than one MMU class configured; use variables. */
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#define L2_S_PROT_U pte_l2_s_prot_u
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#define L2_S_PROT_W pte_l2_s_prot_w
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#define L2_S_PROT_MASK pte_l2_s_prot_mask
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#define L1_S_PROTO pte_l1_s_proto
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#define L1_C_PROTO pte_l1_c_proto
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#define L2_S_PROTO pte_l2_s_proto
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#elif ARM_MMU_GENERIC == 1
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#define L2_S_PROT_U L2_S_PROT_U_generic
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#define L2_S_PROT_W L2_S_PROT_W_generic
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#define L2_S_PROT_MASK L2_S_PROT_MASK_generic
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#define L1_S_PROTO L1_S_PROTO_generic
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#define L1_C_PROTO L1_C_PROTO_generic
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#define L2_S_PROTO L2_S_PROTO_generic
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#elif ARM_MMU_XSCALE == 1
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#define L2_S_PROT_U L2_S_PROT_U_xscale
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#define L2_S_PROT_W L2_S_PROT_W_xscale
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#define L2_S_PROT_MASK L2_S_PROT_MASK_xscale
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#define L1_S_PROTO L1_S_PROTO_xscale
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#define L1_C_PROTO L1_C_PROTO_xscale
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#define L2_S_PROTO L2_S_PROTO_xscale
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#endif /* ARM_NMMUS > 1 */
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/*
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* These macros return various bits based on kernel/user and protection.
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@ -259,18 +396,6 @@ extern vaddr_t pmap_curmaxkvaddr;
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#define L2_S_PROT(ku, pr) ((((ku) == PTE_USER) ? L2_S_PROT_U : 0) | \
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(((pr) & VM_PROT_WRITE) ? L2_S_PROT_W : 0))
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extern pt_entry_t pte_cache_mode;
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/*
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* The following macros are used to construct prototype PTEs.
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*/
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#define L1_S_PROTO (L1_TYPE_S | L1_S_IMP) /* XXX IMP */
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#define L1_C_PROTO (L1_TYPE_C | L1_C_IMP2) /* XXX IMP */
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#define L2_L_PROTO (L2_TYPE_L)
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#define L2_S_PROTO (L2_TYPE_S)
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#endif /* _KERNEL */
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#endif /* _ARM32_PMAP_H_ */
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