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NetBSD/sys/arch/arm/include/cpufunc.h

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Changing the interrupt mask is a scheduling barrier.
2004-08-07 15:47:58 +04:00
/* $NetBSD: cpufunc.h,v 1.31 2004/08/07 11:47:58 rearnsha Exp $ */
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
/*
* Copyright (c) 1997 Mark Brinicombe.
* Copyright (c) 1997 Causality Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Causality Limited.
* 4. The name of Causality Limited may not be used to endorse or promote
* products derived from this software without specific prior written
* permission.
*
* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RiscBSD kernel project
*
* cpufunc.h
*
* Prototypes for cpu, mmu and tlb related functions.
*/
#ifndef _ARM32_CPUFUNC_H_
#define _ARM32_CPUFUNC_H_
#ifdef _KERNEL
Centralize ARM CPU configuration information by adding a new header file, <arm/cpuconf.h>, which pulls in "opt_cputypes.h" and then defines the following: * CPU_NTYPES -- now many CPU types are configured into the kernel. What you really want to know is "== 1" or "> 1". * Defines ARM_ARCH_2, ARM_ARCH_3, ARM_ARCH_4, ARM_ARCH_5, depending on which ARM architecture versions are configured (based on CPU_* options). Also defines ARM_NARCH to determins how many architecture versions are configured. * Defines ARM_MMU_MEMC, ARM_MMU_GENERIC, ARM_MMU_XSCALE depending on which classes of ARM MMUs are configured into the kernel, and ARM_NMMUS to determine how many MMU classes are configured. Remove the needless inclusion of "opt_cputypes.h" in several places. Convert remaining users to <arm/cpuconf.h>.
2002-04-12 22:50:29 +04:00
#include <sys/types.h>
#include <arm/cpuconf.h>
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
struct cpu_functions {
/* CPU functions */
u_int (*cf_id) __P((void));
Add a "cpwait" cpufunc, currently a nullop on all but XScale. "cpwait" ensures that all coprocessor operations have completed before returning.
2001-11-19 21:40:15 +03:00
void (*cf_cpwait) __P((void));
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
/* MMU functions */
u_int (*cf_control) __P((u_int bic, u_int eor));
void (*cf_domains) __P((u_int domains));
void (*cf_setttb) __P((u_int ttb));
u_int (*cf_faultstatus) __P((void));
u_int (*cf_faultaddress) __P((void));
/* TLB functions */
void (*cf_tlb_flushID) __P((void));
void (*cf_tlb_flushID_SE) __P((u_int va));
void (*cf_tlb_flushI) __P((void));
void (*cf_tlb_flushI_SE) __P((u_int va));
void (*cf_tlb_flushD) __P((void));
void (*cf_tlb_flushD_SE) __P((u_int va));
Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
2002-01-25 22:19:22 +03:00
/*
* Cache operations:
*
* We define the following primitives:
*
* icache_sync_all Synchronize I-cache
* icache_sync_range Synchronize I-cache range
*
* dcache_wbinv_all Write-back and Invalidate D-cache
* dcache_wbinv_range Write-back and Invalidate D-cache range
* dcache_inv_range Invalidate D-cache range
* dcache_wb_range Write-back D-cache range
*
* idcache_wbinv_all Write-back and Invalidate D-cache,
* Invalidate I-cache
* idcache_wbinv_range Write-back and Invalidate D-cache,
* Invalidate I-cache range
*
* Note that the ARM term for "write-back" is "clean". We use
* the term "write-back" since it's a more common way to describe
* the operation.
*
* There are some rules that must be followed:
*
* I-cache Synch (all or range):
* The goal is to synchronize the instruction stream,
* so you may beed to write-back dirty D-cache blocks
* first. If a range is requested, and you can't
* synchronize just a range, you have to hit the whole
* thing.
*
* D-cache Write-Back and Invalidate range:
* If you can't WB-Inv a range, you must WB-Inv the
* entire D-cache.
*
* D-cache Invalidate:
* If you can't Inv the D-cache, you must Write-Back
* and Invalidate. Code that uses this operation
* MUST NOT assume that the D-cache will not be written
* back to memory.
*
* D-cache Write-Back:
* If you can't Write-back without doing an Inv,
* that's fine. Then treat this as a WB-Inv.
* Skipping the invalidate is merely an optimization.
*
* All operations:
* Valid virtual addresses must be passed to each
* cache operation.
*/
void (*cf_icache_sync_all) __P((void));
void (*cf_icache_sync_range) __P((vaddr_t, vsize_t));
void (*cf_dcache_wbinv_all) __P((void));
void (*cf_dcache_wbinv_range) __P((vaddr_t, vsize_t));
void (*cf_dcache_inv_range) __P((vaddr_t, vsize_t));
void (*cf_dcache_wb_range) __P((vaddr_t, vsize_t));
void (*cf_idcache_wbinv_all) __P((void));
void (*cf_idcache_wbinv_range) __P((vaddr_t, vsize_t));
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
/* Other functions */
void (*cf_flush_prefetchbuf) __P((void));
void (*cf_drain_writebuf) __P((void));
void (*cf_flush_brnchtgt_C) __P((void));
void (*cf_flush_brnchtgt_E) __P((u_int va));
void (*cf_sleep) __P((int mode));
/* Soft functions */
int (*cf_dataabt_fixup) __P((void *arg));
int (*cf_prefetchabt_fixup) __P((void *arg));
void (*cf_context_switch) __P((void));
void (*cf_setup) __P((char *string));
};
extern struct cpu_functions cpufuncs;
extern u_int cputype;
#define cpu_id() cpufuncs.cf_id()
Add a "cpwait" cpufunc, currently a nullop on all but XScale. "cpwait" ensures that all coprocessor operations have completed before returning.
2001-11-19 21:40:15 +03:00
#define cpu_cpwait() cpufuncs.cf_cpwait()
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#define cpu_control(c, e) cpufuncs.cf_control(c, e)
#define cpu_domains(d) cpufuncs.cf_domains(d)
#define cpu_setttb(t) cpufuncs.cf_setttb(t)
#define cpu_faultstatus() cpufuncs.cf_faultstatus()
#define cpu_faultaddress() cpufuncs.cf_faultaddress()
#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
2002-01-25 22:19:22 +03:00
#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
#define cpu_sleep(m) cpufuncs.cf_sleep(m)
#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
Fix typo in comment (suceed).
2001-08-20 15:49:11 +04:00
#define ABORT_FIXUP_OK 0 /* fixup succeeded */
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#define ABORT_FIXUP_FAILED 1 /* fixup failed */
#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
#define cpu_setup(a) cpufuncs.cf_setup(a)
int set_cpufuncs __P((void));
#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
void cpufunc_nullop __P((void));
Create cpufunc_null_fixup() to replace all the CPU-specific abort-fixup routines that did nothing.
2001-03-07 01:29:13 +03:00
int cpufunc_null_fixup __P((void *));
Replace arm6_dataabt_fixup() and arm7_dataabt_fixup() with early_abort_fixup() and late_abort_fixup(), based on the abort model in use, rather than the CPU type. This cleans up the code and makes it smaller. Only tested on an ARM6 -- I can't find my ARM710a card right now.
2001-06-03 01:03:32 +04:00
int early_abort_fixup __P((void *));
int late_abort_fixup __P((void *));
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
u_int cpufunc_id __P((void));
u_int cpufunc_control __P((u_int clear, u_int bic));
void cpufunc_domains __P((u_int domains));
u_int cpufunc_faultstatus __P((void));
u_int cpufunc_faultaddress __P((void));
Initial cpufunc operations for ARM3. Not actually used yet.
2001-06-02 23:01:03 +04:00
#ifdef CPU_ARM3
u_int arm3_control __P((u_int clear, u_int bic));
void arm3_cache_flush __P((void));
#endif /* CPU_ARM3 */
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#if defined(CPU_ARM6) || defined(CPU_ARM7)
void arm67_setttb __P((u_int ttb));
void arm67_tlb_flush __P((void));
void arm67_tlb_purge __P((u_int va));
void arm67_cache_flush __P((void));
void arm67_context_switch __P((void));
#endif /* CPU_ARM6 || CPU_ARM7 */
#ifdef CPU_ARM6
void arm6_setup __P((char *string));
#endif /* CPU_ARM6 */
#ifdef CPU_ARM7
void arm7_setup __P((char *string));
#endif /* CPU_ARM7 */
Add support for ARM7TDMI, as provided in a patch from John Fremlin to port-arm32. Shouldn't effect any currently in tree ports.
2001-06-03 22:32:33 +04:00
#ifdef CPU_ARM7TDMI
int arm7_dataabt_fixup __P((void *arg));
void arm7tdmi_setup __P((char *string));
void arm7tdmi_setttb __P((u_int ttb));
void arm7tdmi_tlb_flushID __P((void));
void arm7tdmi_tlb_flushID_SE __P((u_int va));
void arm7tdmi_cache_flushID __P((void));
void arm7tdmi_context_switch __P((void));
#endif /* CPU_ARM7TDMI */
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#ifdef CPU_ARM8
void arm8_setttb __P((u_int ttb));
void arm8_tlb_flushID __P((void));
void arm8_tlb_flushID_SE __P((u_int va));
void arm8_cache_flushID __P((void));
void arm8_cache_flushID_E __P((u_int entry));
void arm8_cache_cleanID __P((void));
void arm8_cache_cleanID_E __P((u_int entry));
void arm8_cache_purgeID __P((void));
void arm8_cache_purgeID_E __P((u_int entry));
void arm8_cache_syncI __P((void));
Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
2002-01-25 22:19:22 +03:00
void arm8_cache_cleanID_rng __P((vaddr_t start, vsize_t end));
void arm8_cache_cleanD_rng __P((vaddr_t start, vsize_t end));
void arm8_cache_purgeID_rng __P((vaddr_t start, vsize_t end));
void arm8_cache_purgeD_rng __P((vaddr_t start, vsize_t end));
void arm8_cache_syncI_rng __P((vaddr_t start, vsize_t end));
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
void arm8_context_switch __P((void));
void arm8_setup __P((char *string));
u_int arm8_clock_config __P((u_int, u_int));
#endif
Use processor specific versions of ARM cache control functions for SA1100 and SA1110 instead of using SA110 ones. Rename common StrongARM functions from sa110_* to sa1_*. Reviewed by Jason Thorpe.
2002-05-03 20:45:21 +04:00
#ifdef CPU_SA110
void sa110_setup __P((char *string));
void sa110_context_switch __P((void));
#endif /* CPU_SA110 */
#if defined(CPU_SA1100) || defined(CPU_SA1110)
void sa11x0_drain_readbuf __P((void));
void sa11x0_context_switch __P((void));
void sa11x0_cpu_sleep __P((int mode));
void sa11x0_setup __P((char *string));
#endif
#if defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110)
void sa1_setttb __P((u_int ttb));
void sa1_tlb_flushID_SE __P((u_int va));
void sa1_cache_flushID __P((void));
void sa1_cache_flushI __P((void));
void sa1_cache_flushD __P((void));
void sa1_cache_flushD_SE __P((u_int entry));
void sa1_cache_cleanID __P((void));
void sa1_cache_cleanD __P((void));
void sa1_cache_cleanD_E __P((u_int entry));
void sa1_cache_purgeID __P((void));
void sa1_cache_purgeID_E __P((u_int entry));
void sa1_cache_purgeD __P((void));
void sa1_cache_purgeD_E __P((u_int entry));
void sa1_cache_syncI __P((void));
void sa1_cache_cleanID_rng __P((vaddr_t start, vsize_t end));
void sa1_cache_cleanD_rng __P((vaddr_t start, vsize_t end));
void sa1_cache_purgeID_rng __P((vaddr_t start, vsize_t end));
void sa1_cache_purgeD_rng __P((vaddr_t start, vsize_t end));
void sa1_cache_syncI_rng __P((vaddr_t start, vsize_t end));
#endif
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
#ifdef CPU_ARM9
void arm9_setttb __P((u_int));
void arm9_tlb_flushID_SE __P((u_int va));
Switch the ARM9 to using the Dcache in write-back mode. Avoid an unknown problem with dcache_inv_range by using a wbinv for now (similarly for ARM10). When setting the ARM9 system control register, use the computed cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are not reset to FastBus mode (which isn't very fast).
2004-01-26 18:54:16 +03:00
void arm9_icache_sync_all __P((void));
void arm9_icache_sync_range __P((vaddr_t, vsize_t));
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
Switch the ARM9 to using the Dcache in write-back mode. Avoid an unknown problem with dcache_inv_range by using a wbinv for now (similarly for ARM10). When setting the ARM9 system control register, use the computed cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are not reset to FastBus mode (which isn't very fast).
2004-01-26 18:54:16 +03:00
void arm9_dcache_wbinv_all __P((void));
void arm9_dcache_wbinv_range __P((vaddr_t, vsize_t));
void arm9_dcache_inv_range __P((vaddr_t, vsize_t));
void arm9_dcache_wb_range __P((vaddr_t, vsize_t));
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
Switch the ARM9 to using the Dcache in write-back mode. Avoid an unknown problem with dcache_inv_range by using a wbinv for now (similarly for ARM10). When setting the ARM9 system control register, use the computed cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are not reset to FastBus mode (which isn't very fast).
2004-01-26 18:54:16 +03:00
void arm9_idcache_wbinv_all __P((void));
void arm9_idcache_wbinv_range __P((vaddr_t, vsize_t));
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
void arm9_context_switch __P((void));
void arm9_setup __P((char *string));
Switch the ARM9 to using the Dcache in write-back mode. Avoid an unknown problem with dcache_inv_range by using a wbinv for now (similarly for ARM10). When setting the ARM9 system control register, use the computed cpuctrlmask value (not 0xffffffff) so that the clocking-mode bits are not reset to FastBus mode (which isn't very fast).
2004-01-26 18:54:16 +03:00
extern unsigned arm9_dcache_sets_max;
extern unsigned arm9_dcache_sets_inc;
extern unsigned arm9_dcache_index_max;
extern unsigned arm9_dcache_index_inc;
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
#endif
Add processor-specific declarations for ARM10 class processors.
2003-09-06 13:08:35 +04:00
#ifdef CPU_ARM10
void arm10_setttb __P((u_int));
void arm10_tlb_flushID_SE __P((u_int));
void arm10_tlb_flushI_SE __P((u_int));
void arm10_icache_sync_all __P((void));
void arm10_icache_sync_range __P((vaddr_t, vsize_t));
void arm10_dcache_wbinv_all __P((void));
void arm10_dcache_wbinv_range __P((vaddr_t, vsize_t));
void arm10_dcache_inv_range __P((vaddr_t, vsize_t));
void arm10_dcache_wb_range __P((vaddr_t, vsize_t));
void arm10_idcache_wbinv_all __P((void));
void arm10_idcache_wbinv_range __P((vaddr_t, vsize_t));
void arm10_context_switch __P((void));
void arm10_setup __P((char *string));
extern unsigned arm10_dcache_sets_max;
extern unsigned arm10_dcache_sets_inc;
extern unsigned arm10_dcache_index_max;
extern unsigned arm10_dcache_index_inc;
#endif
#if defined(CPU_ARM9) || defined(CPU_ARM10) || defined(CPU_SA110) || \
defined(CPU_SA1100) || defined(CPU_SA1110) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
Use processor specific versions of ARM cache control functions for SA1100 and SA1110 instead of using SA110 ones. Rename common StrongARM functions from sa110_* to sa1_*. Reviewed by Jason Thorpe.
2002-05-03 20:45:21 +04:00
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
void armv4_tlb_flushID __P((void));
void armv4_tlb_flushI __P((void));
void armv4_tlb_flushD __P((void));
void armv4_tlb_flushD_SE __P((u_int va));
void armv4_drain_writebuf __P((void));
#endif
add support for ixp12x0
2002-07-15 20:27:15 +04:00
#if defined(CPU_IXP12X0)
void ixp12x0_drain_readbuf __P((void));
void ixp12x0_context_switch __P((void));
void ixp12x0_setup __P((char *string));
#endif
Add support for the Intel PXA210 and PXA250. From Hiroyuki Bessho, PR 16617.
2002-05-03 07:28:48 +04:00
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
support IXP425 Intel Network Processor running on BigEndian
2003-05-23 04:57:23 +04:00
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425)
Add a "cpwait" cpufunc, currently a nullop on all but XScale. "cpwait" ensures that all coprocessor operations have completed before returning.
2001-11-19 21:40:15 +03:00
void xscale_cpwait __P((void));
Two changes for XScale: 1) Add defparam XSCALE_CCLKCFG to define a parameter for the CCLKCFG register. Default it to '9' on the IQ80310. 2) Add a sleep call to the xscale CPU function vector (replacing the nullop) which should drop the CPU into "idle" mode when cpu_switch finds nothing on the run queues.
2002-01-24 07:23:18 +03:00
void xscale_cpu_sleep __P((int mode));
* Give the XScale its own cpu_control() entry point; we have to flush the Branch Target Buffer of the BPRD bit changes. * Enable Branch Prediction on the XScale by default. * Don't invalidate the Branch Target Buffer explicitly. the i80200 manual (section 5.1, Branch Target Buffer Operation) notes that manual software management of the BTB is unnecessary; it is flushed implicitly when: * processor resets * FCSE process ID is written * I-cache is invalidated
2001-11-14 04:00:05 +03:00
u_int xscale_control __P((u_int clear, u_int bic));
Add xscale cpu functions
2001-08-26 23:41:57 +04:00
void xscale_setttb __P((u_int ttb));
Add support calls for ARM9. Where ARM9, StrongARM and XScale share the same function, rename it as armv4_XXX.
2001-10-18 18:10:07 +04:00
Add xscale cpu functions
2001-08-26 23:41:57 +04:00
void xscale_tlb_flushID_SE __P((u_int va));
void xscale_cache_flushID __P((void));
void xscale_cache_flushI __P((void));
void xscale_cache_flushD __P((void));
void xscale_cache_flushD_SE __P((u_int entry));
void xscale_cache_cleanID __P((void));
void xscale_cache_cleanD __P((void));
void xscale_cache_cleanD_E __P((u_int entry));
* Move the code that cleans the XScale mini-data cache into its own function. * Add a new function which sets up the mini-data cache clean area properly.
2002-04-10 03:44:00 +04:00
void xscale_cache_clean_minidata __P((void));
Add xscale cpu functions
2001-08-26 23:41:57 +04:00
void xscale_cache_purgeID __P((void));
void xscale_cache_purgeID_E __P((u_int entry));
void xscale_cache_purgeD __P((void));
void xscale_cache_purgeD_E __P((u_int entry));
void xscale_cache_syncI __P((void));
Overhaul of the ARM cache code. This is mostly a simplification pass. Rather than providing a whole slew of cache operations that aren't ever used, distill them down to some useful primitives: icache_sync_all Synchronize I-cache icache_sync_range Synchronize I-cache range dcache_wbinv_all Write-back and Invalidate D-cache dcache_wbinv_range Write-back and Invalidate D-cache range dcache_inv_range Invalidate D-cache range dcache_wb_range Write-back D-cache range idcache_wbinv_all Write-back and Invalidate D-cache, Invalidate I-cache idcache_wbinv_range Write-back and Invalidate D-cache, Invalidate I-cache range Note: This does not yet include an overhaul of the actual asm files that implement the primitives. Instead, we've provided a safe default for each CPU type, and the individual CPU types can now be optimized one at a time.
2002-01-25 22:19:22 +03:00
void xscale_cache_cleanID_rng __P((vaddr_t start, vsize_t end));
void xscale_cache_cleanD_rng __P((vaddr_t start, vsize_t end));
void xscale_cache_purgeID_rng __P((vaddr_t start, vsize_t end));
void xscale_cache_purgeD_rng __P((vaddr_t start, vsize_t end));
void xscale_cache_syncI_rng __P((vaddr_t start, vsize_t end));
void xscale_cache_flushD_rng __P((vaddr_t start, vsize_t end));
Add prototypes for new XScale write-through cache routines.
2001-11-28 03:18:46 +03:00
Add xscale cpu functions
2001-08-26 23:41:57 +04:00
void xscale_context_switch __P((void));
void xscale_setup __P((char *string));
support IXP425 Intel Network Processor running on BigEndian
2003-05-23 04:57:23 +04:00
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425 */
Add xscale cpu functions
2001-08-26 23:41:57 +04:00
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#define tlb_flush cpu_tlb_flushID
#define setttb cpu_setttb
#define drain_writebuf cpu_drain_writebuf
/*
* Macros for manipulating CPU interrupts
*/
* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
2001-12-20 04:20:21 +03:00
#ifdef __PROG32
Inline SetCPSR calls where it seems prudent to do so. This avoids two branches and allows the compiler to better utilize registers around calls to disable/enable/restore_interrupts().
2002-08-15 01:55:52 +04:00
static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
static __inline u_int32_t
__set_cpsr_c(u_int bic, u_int eor)
{
u_int32_t tmp, ret;
__asm __volatile(
"mrs %0, cpsr\n" /* Get the CPSR */
"bic %1, %0, %2\n" /* Clear bits */
"eor %1, %1, %3\n" /* XOR bits */
"msr cpsr_c, %1\n" /* Set the control field of CPSR */
: "=&r" (ret), "=&r" (tmp)
Changing the interrupt mask is a scheduling barrier.
2004-08-07 15:47:58 +04:00
: "r" (bic), "r" (eor) : "memory");
Inline SetCPSR calls where it seems prudent to do so. This avoids two branches and allows the compiler to better utilize registers around calls to disable/enable/restore_interrupts().
2002-08-15 01:55:52 +04:00
return ret;
}
* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
2001-12-20 04:20:21 +03:00
#define disable_interrupts(mask) \
Inline SetCPSR calls where it seems prudent to do so. This avoids two branches and allows the compiler to better utilize registers around calls to disable/enable/restore_interrupts().
2002-08-15 01:55:52 +04:00
(__set_cpsr_c((mask) & (I32_bit | F32_bit), \
(mask) & (I32_bit | F32_bit)))
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
2001-12-20 04:20:21 +03:00
#define enable_interrupts(mask) \
Inline SetCPSR calls where it seems prudent to do so. This avoids two branches and allows the compiler to better utilize registers around calls to disable/enable/restore_interrupts().
2002-08-15 01:55:52 +04:00
(__set_cpsr_c((mask) & (I32_bit | F32_bit), 0))
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
2001-12-20 04:20:21 +03:00
#define restore_interrupts(old_cpsr) \
Inline SetCPSR calls where it seems prudent to do so. This avoids two branches and allows the compiler to better utilize registers around calls to disable/enable/restore_interrupts().
2002-08-15 01:55:52 +04:00
(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
* Share a common vector page between arm26 and arm32. * Use a common set of exception handlers for all arm32 platforms. * New FIQ framework based on discussions with Ben Harris, shared between arm26 and arm32.
2001-12-20 04:20:21 +03:00
#else /* ! __PROG32 */
#define disable_interrupts(mask) \
(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
(mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
#define enable_interrupts(mask) \
(set_r15((mask) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE), 0))
#define restore_interrupts(old_r15) \
(set_r15((R15_IRQ_DISABLE | R15_FIQ_DISABLE), \
(old_r15) & (R15_IRQ_DISABLE | R15_FIQ_DISABLE)))
#endif /* __PROG32 */
#ifdef __PROG32
/* Functions to manipulate the CPSR. */
u_int SetCPSR(u_int bic, u_int eor);
u_int GetCPSR(void);
#else
/* Functions to manipulate the processor control bits in r15. */
u_int set_r15(u_int bic, u_int eor);
u_int get_r15(void);
#endif /* __PROG32 */
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
/*
* Functions to manipulate cpu r13
Add xscale cpu functions
2001-08-26 23:41:57 +04:00
* (in arm/arm32/setstack.S)
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
*/
void set_stackptr __P((u_int mode, u_int address));
u_int get_stackptr __P((u_int mode));
Add get_pc_str_offset(), which returns the offset between the address of an instruction that stores the program counter and the value of PC that's stored. This can vary between ARM implementations, but is guaranteed to be constant on a given one.
2001-06-05 13:19:32 +04:00
/*
* Miscellany
*/
Make the declaration of get_pc_str_offset() into a prototype.
2001-10-14 04:17:26 +04:00
int get_pc_str_offset __P((void));
Add get_pc_str_offset(), which returns the offset between the address of an instruction that stores the program counter and the value of PC that's stored. This can vary between ARM implementations, but is guaranteed to be constant on a given one.
2001-06-05 13:19:32 +04:00
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
/*
* CPU functions from locore.S
*/
void cpu_reset __P((void)) __attribute__((__noreturn__));
Fetch cache info from the Cache Type register on ARM7TDMI and "greater" processors. Report this when the processor is attached.
2001-11-29 05:24:58 +03:00
/*
* Cache info variables.
*/
/* PRIMARY CACHE VARIABLES */
Fix declarations of primary cache variables, so that they are declarations, not definitions.
2003-09-06 13:04:52 +04:00
extern int arm_picache_size;
extern int arm_picache_line_size;
extern int arm_picache_ways;
Fetch cache info from the Cache Type register on ARM7TDMI and "greater" processors. Report this when the processor is attached.
2001-11-29 05:24:58 +03:00
Fix declarations of primary cache variables, so that they are declarations, not definitions.
2003-09-06 13:04:52 +04:00
extern int arm_pdcache_size; /* and unified */
extern int arm_pdcache_line_size;
extern int arm_pdcache_ways;
Fetch cache info from the Cache Type register on ARM7TDMI and "greater" processors. Report this when the processor is attached.
2001-11-29 05:24:58 +03:00
Fix declarations of primary cache variables, so that they are declarations, not definitions.
2003-09-06 13:04:52 +04:00
extern int arm_pcache_type;
extern int arm_pcache_unified;
Fetch cache info from the Cache Type register on ARM7TDMI and "greater" processors. Report this when the processor is attached.
2001-11-29 05:24:58 +03:00
Fix declarations of primary cache variables, so that they are declarations, not definitions.
2003-09-06 13:04:52 +04:00
extern int arm_dcache_align;
extern int arm_dcache_align_mask;
Fetch cache info from the Cache Type register on ARM7TDMI and "greater" processors. Report this when the processor is attached.
2001-11-29 05:24:58 +03:00
Big patch for merging common include files of the new hpcarm tree and the old arm32 tree into the new arm substree. All moved files are relinked with a stub that included the file from the new location; this might be done better later.
2001-02-24 00:23:45 +03:00
#endif /* _KERNEL */
#endif /* _ARM32_CPUFUNC_H_ */
/* End of cpufunc.h */
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