Commit Graph

2214 Commits

Author SHA1 Message Date
lazymio
35017a614f
Slightly change UC_CTL_TB_REMOVE_CACHE 2021-11-08 22:09:33 +01:00
lazymio
6ec016327d
Rename uc_hook_tcg_sub_t 2021-11-08 21:01:47 +01:00
lazymio
4df0ad5e83
Update docs for exits mechanism 2021-11-08 20:54:07 +01:00
lazymio
e836b62e01
Minor fix for uc_ctl 2021-11-08 20:40:02 +01:00
lazymio
06f454d513
Update CMakeLists to use it as subproject 2021-11-07 21:07:53 +01:00
lazymio
9abbba173c
Update python bindings 2021-11-07 21:00:05 +01:00
lazymio
bfb5875eb9
Update rust CI 2021-11-07 20:58:51 +01:00
lazymio
2f61592ff9
Fix uc_mem_protect 2021-11-07 20:37:58 +01:00
lazymio
c6fdbb3735
Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
George Hotz
7268c2a19b
mips: support reading and writing of hi/lo regs 2021-11-07 20:27:02 +01:00
George Hotz
8732cff287
add rpath and go.mod 2021-11-07 20:24:50 +01:00
lazymio
94a82ed94d
Ensure JIT protection is disabled when generating TB 2021-11-07 20:23:25 +01:00
lazymio
923b4ad3cc
Update python bindings 2021-11-04 21:47:30 +01:00
lazymio
cd02c25802
Fix bug in remove cache and update comments 2021-11-04 21:29:55 +01:00
lazymio
a9bfa0afb0
Update comments 2021-11-04 21:22:49 +01:00
lazymio
96fc0bf6bc
Fix typo in sample 2021-11-04 21:10:31 +01:00
lazymio
01d7e454b7
Fix typo 2021-11-04 20:59:07 +01:00
lazymio
1507f90059
Fix name typo 2021-11-04 20:07:01 +01:00
lazymio
b9c0066a47
Format and naming 2021-11-04 20:04:57 +01:00
lazymio
db90f39ac6
Generate bindings 2021-11-04 20:01:19 +01:00
lazymio
025e32df4a
Init uc on cpu model read 2021-11-04 20:00:01 +01:00
lazymio
613ddf0985
Format 2021-11-04 19:58:44 +01:00
lazymio
871de4ad65
Split mips cpu to 32 and 64 2021-11-04 19:58:32 +01:00
lazymio
0555095388
Support changing cpu model for ppc 2021-11-04 19:53:02 +01:00
lazymio
e5a2eae173
Add comment for default cpu model 2021-11-04 19:22:50 +01:00
lazymio
64452e249d
Support changing cpu model for sparc 2021-11-04 19:22:08 +01:00
lazymio
b0280f5e55
Support changing cpu model for m68k 2021-11-04 19:16:35 +01:00
lazymio
172a2fbe6d
Support changing cpu model for riscv 2021-11-04 19:13:53 +01:00
lazymio
435ac71f47
Support changing cpu model for x86 2021-11-04 19:10:29 +01:00
lazymio
837c3be347
Support changing cpu model for MIPS 2021-11-04 19:05:56 +01:00
lazymio
94d952b410
Add depreciated in unicorn.h 2021-11-04 18:44:56 +01:00
lazymio
937445466b
Update samples to show the use of uc_ctl 2021-11-04 18:41:45 +01:00
lazymio
3aa2788586
Format 2021-11-04 18:39:52 +01:00
lazymio
ebe1f83293
Initialize UC when reading page size 2021-11-04 18:39:38 +01:00
lazymio
dfbffa44ec
Support changing cpu model for ARM 2021-11-04 18:37:10 +01:00
lazymio
28013c13be
Don't init on page size read 2021-11-04 18:29:42 +01:00
lazymio
3e4b4af7d3
Support change page size 2021-11-04 17:03:30 +01:00
lazymio
3ead1731fe
Also instrument sub2
In this case, users don't need to care about the stuble difference inside tcg opcode
2021-11-03 23:48:09 +01:00
lazymio
ad2480f32c
Enable verbose test output 2021-11-03 21:44:00 +01:00
lazymio
67e2386da6
Add test and close #1477 2021-11-03 21:40:13 +01:00
lazymio
1a82248292
Add test for #992 2021-11-03 21:17:57 +01:00
lazymio
3dfec280c7
Merge and close #1161 2021-11-03 21:02:48 +01:00
lazymio
6b5529fcb7
Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
2021-11-03 20:59:42 +01:00
lazymio
9818840f4e
Add tests for UC_HOOK_TCG_OPCODE 2021-11-03 20:56:45 +01:00
lazymio
58edb2abe7
Format 2021-11-03 13:28:12 +01:00
lazymio
09aa0f944f
Merge QDucasse:riscv_extension_d
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
2021-11-03 13:20:46 +01:00
lazymio
bcf85be86d
Add a new hook type UC_HOOK_TCG_OPCODE 2021-11-03 01:46:24 +01:00
lazymio
eb75d459f0
Add a regression test for invalidating empty TB and have a better solution 2021-11-03 01:07:06 +01:00
Bet4
aaf340d9e4 Merge branch 'dev' into patch 2021-11-02 18:36:22 +08:00
lazymio
c11b9aa5c3
Add a new hook type UC_HOOK_EDGE_GENERATED and corresponding sample 2021-11-01 23:27:35 +01:00