Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier
flags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actual
functions to op_helper.c.
Thanks to Igor Kovalenko for reporting.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Calculate only the carry flag for ADDX/SUBX instead of full
set of flags.
Thanks to Igor Kovalenko for spotting a bug with an earlier
version.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix errors missed in 2065061ede:
CC sparc64-softmmu/helper.o
cc1: warnings being treated as errors
/src/qemu/target-sparc/helper.c: In function 'get_physical_address':
/src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function
/src/qemu/target-sparc/helper.c:426: note: 'context' was declared here
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- increase max supported MMU modes to 6
- handle nucleus context asi
- handle secondary context asi
- handle non-faulting loads from secondary context
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- match global tte against any context
- show global tte in MMU dump
v0->v1: added default case to switch statement in demap_tlb
- should fix gcc warning about uninitialized context variable
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Single-stepping was not properly updating npc, resulting in some
instructions being executed twice. In addition, we were emitting
dead code at the end of the TB.
Fix both by teaching gen_goto_tb to avoid goto_tb for single-step
and removing the special-case code in gen_intermediate_code_internal.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use address_mask on both addr and addr+8 in both these routines,
rather than explicit masking with 0xffffffff.
Reformulate address_mask to return a result, rather than masking
a pass-by-reference argument.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
These clang errors are harmless but worth fixing:
CC ppc-softmmu/usb-ohci.o
/src/qemu/hw/usb-ohci.c:1104:59: error: if statement has empty body [-Wempty-body]
ohci->ctrl_head, ohci->ctrl_cur);
/src/qemu/hw/usb-ohci.c:1371:57: error: if statement has empty body [-Wempty-body]
DPRINTF("usb-ohci: port %d: SUSPEND\n", portnum);
CC sparc64-softmmu/translate.o
/src/qemu/target-sparc/translate.c:3173:37: error: if statement has empty body [-Wempty-body]
; // XXX
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Rather than creating new temporaries for constants, use the
ones created in disas_sparc_insn. Remember the temps created
there so that they can be freed at the end of the function.
Profile data collected by TCG while booting sparc-test kernel:
-avg temps/TB 70.61 max=421
+avg temps/TB 62.75 max=66
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The 32 and 64-bit definitions were swapped in the ifdef.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix a case where an exception happens with the
instruction in the delay slot.
Recovery of branch condition in the exception handling
code was not converted to TCG. Because the condition
was bogus, wrong NPC could be selected from the two
candidates.
A nice bug report with a test case can be found in:
https://bugs.launchpad.net/qemu/+bug/551814
Fix based on patch by Fabrice Bellard.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
QEMU uses a fixed page size for the CPU TLB. If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.
When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page. However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.
Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages. If the guest invalidates this region then flush the
whole TLB.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Removes a set of ifdefs from exec.c.
Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha. This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.
Signed-off-by: Richard Henderson <rth@twiddle.net>
b551ec04ca fixed
the compilation for 32 bit hosts, but introduced
a new error for 64 bit hosts:
tcg_temp_new_ptr needs a matching tcg_temp_free_ptr.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use 32-bit arithmetic for the address offset calculation to fix a
build failure on 32-bit hosts.
Signed-off-by: Jay Foad <jay.foad@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
if the access check fails, the page can not be modified
and shouldn't be marked dirty.
The patch fixes the "hsfs_putpage: dirty HSFS page"
error in Solaris guests.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
sparc64 timer has tick counter which can be set and read,
and tick compare value used as deadline to fire timer interrupt.
The timer is not used as periodic timer, instead deadline
is set each time new timer interrupt is needed.
v3 -> v4:
- coding style
v2 -> v3:
- added missing timer debug output macro
- CPUTimer struct and typedef moved to cpu.h
- change CPU_SAVE_VERSION to 6, older save formats not supported
v1 -> v2:
- new conversion helpers cpu_to_timer_ticks and timer_to_cpu_ticks
- save offset from clock source to implement cpu_tick_set_count
- renamed struct sun4u_timer to CPUTimer
- load and save cpu timers
v0 -> v1:
- coding style
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- correctly fit to cwp if provided window number is out of range
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Common:
* Remove unnecessary 0x prefix
* Print %y
* Fix NZVC flag print order to match CPU bit order
Sparc64 specific:
* Print registers without line wrapping
* Print %f40-%f63
* Pretty print CCR flags
* Print %fsr and %fprs in full precision
* More consistent formatting
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
According to pages 9-31 - 9-34 of "SuperSPARC & MultiCache Controller
User's Manual":
1. "A lower priority fault may not overwrite the
MFSR status of a higher priority fault."
2. The MFAR is overwritten according to the policy defined for the MFSR
3. The overwrite bit is asserted if the fault status register (MFSR)
has been written more than once by faults of the same class
4. SuperSPARC will never place instruction fault addresses in the MFAR.
Implementation of points 1-3 allows booting Solaris 2.6 and 2.5.1.
v2: CODING_STYLE fixes
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu_check_irqs
- handle SOFTINT register TICK and STICK timer bits
- only check interrupt levels greater than PIL value
- handle preemption by higher level traps
cpu_exec
- handle CPU_INTERRUPT_HARD only if interrupts are enabled
- PIL 15 is not special level on sparcv9
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- pstate is 32bit variable, no need to pass 64bit value around
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- this fixes stepping with gdb, where do_unassigned_access
may be called from gdb handler, outside of generated code
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
- extended range of MMU related traps which use MMU global registers,
as listed in Ultrasparc-IIi document
- no visible changes, since emulation do not cause added traps
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
The page 108 of the SPARC Version 8 Architecture Manual describes
that addcc and addxcc shall compute carry flag the same way.
The page 110 claims the same about subcc and subxcc instructions.
This patch fixes carry computation in corner cases and removes redundant code.
The most visible effect of the patch is enabling Solaris boot when using OBP.
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
[blauwirbel@gmail.com: cleaned up formatting]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Fix done instruction to resume with pc=tnpc, npc=tnpc+4
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
In the very least, a change like this requires discussion on the list.
The naming convention is goofy and it causes a massive merge problem. Something
like this _must_ be presented on the list first so people can provide input
and cope with it.
This reverts commit 99a0949b72.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Sparc64 alternate space load/store helpers expect 8 bit ASI value,
while wrasi implementation sign-extends ASI operand causing
for example 0x80 to appear as 0xFFFFFF80. Resulting value falls
out of switch in helpers and causes obscure load/store faults.
- correct wrasi by masking lower 8 bits of xor result
- use lower 8 bits of ASI register in helpers
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.
Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations. This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently. Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.
Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality. I have removed
such blocks for the appropriate targets in this patch.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding
trap level.
This patch removes tsptr from sparc64 cpu state and replaces
all uses with call to helper routine.
Changes v0->v1:
- reimplemented helper routine with tcg generator
- on cpu reset trap type and pstate are populated with power-on reset
values, including tl=maxtl
Signed-off-by: igor.v.kovalenko@gmail.com
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
If translation block is interrupted by e.g. mmu exception
we need to compute conditional flags for inclusion into
saved cpu state. Otherwise after return from trap
conditional instructions would use stale psr/xcc data.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
- implement "used" bit in tlb translation entry
- mark tlb entry used if qemu code/data translation succeeds
- fold i/d mmu replacement writes code into replace_tlb_1bit_lru which
adds 1bit lru replacement algorithm; previously code tried to replace
first unlocked entry only
- extract more bitmasks to named macros
- add "immu" or "dmmu" type name to debugging output where appropriate
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
- add names to mmu registers, this helps understanding the code which
uses/modifies them.
- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries
- extract demap_tlb routine (code duplication)
- extract replace_tlb routine (code duplication)
- flush qemu tlb translations when replacing sparc64 mmu tlb entries
I have no test case which demands flushing qemu translations,
and this patch should have no other visible changes to runtime.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
I used the following command to enable debugging:
perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/*
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Good trap handling is required to process interrupts.
>> This patch fixes the following:
>>
>> - sparc64 has no wim register
>> - sparc64 has no psret register, use IE bit of pstate
>> extract IE checking code to cpu_interrupts_enabled
>> - alternate globals are not available if cpu has GL feature
>> in this case bit AG of pstate is constant zero
>> - write to pstate must actually write pstate
>> even if cpu has GL feature
>>
>> Also timer interrupt is handled using do_interrupt.
>
> A bit too much for one patch. Please also remove the code instead of
> commenting out.
I now excluded timer interrupt related part.
To my mind other changes are essentially tied together.
> PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.
Fixed, please find attached the updated version.
--
Kind regards,
Igor V. Kovalenko
On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
> On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
>> It is clear that intention is to byte-swap value to be written, not
>> the target address.
>
> @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta
> case 0x89: // Secondary LE
> switch(size) {
> case 2:
> - addr = bswap16(addr);
> + addr = bswap16(val);
> ^^^^
> Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and
> 64-bit cases)? Also needs a 'signed-off-by:'...
>
> Cheers,
> --
> Stuart Brady
>
Thanks, that part I did not runtime-tested.
Not sure if those asi stores are of any use for user-mode emulator.
Please find attached the corrected version.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
This patch extracts common part of sparc64 tag
matching code used by IMMU and DMMU lookups.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
This Implement physical address truncation in mmu bypass mode.
IMMU bypass is also active when cpu enters RED_STATE
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
The only target dependency for most hardware is sizeof(target_phys_addr_t).
Build these files into a convenience library, and use that instead of
building for every target.
Remove and poison various target specific macros to avoid bogus target
dependencies creeping back in.
Big/Little endian is not handled because devices should not know or care
about this to start with.
Signed-off-by: Paul Brook <paul@codesourcery.com>
Include assert.h from qemu-common.h and remove other direct uses.
cpu-all.h still need to include it because of the dyngen-exec.h hacks
Signed-off-by: Paul Brook <paul@codesourcery.com>
Revert previous change to get_physical_address_code:
I/D MMU context register is shared, so using dmmuregs[1] is correct
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
TLB match code must respect page size, otherwise 4M page mappings may
be not found.
Also correct a typo in get_physical_address_code which should use IMMU
registers.
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
--
Kind regards,
Igor V. Kovalenko
Posting updated patch to the list...
>>> On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote:
>>> >
>>> > Nice, though I didn't notice any visible improvement in my tests.
>>>
>>> This early in boot process there is not much to output; and I test
>>> recent kernel which may use different startup sequence.
>>> I modified openbios cif handler to output arguments and I now can see
>>> visible difference.
>>>
>>>
>>> >
>>> > About the patch, there are a few problems:
>>> > - it breaks Sparc32
>>>
>>> You mean it stops working?
>>
>> Does not even build.
Fixed now.
>>> > - commented out code is ugly
>>> > - if and else should be on the same line as '{' or '}'
>>> > - long lines should be wrapped
>>> > - in the line:
>>> > + return (((tag_access_register & 0x1fff)<<48)|(tag_access_register >> 22));
>>> > there should be white space between ) and << and 48.
>>> >
>>>
>>
>> Also the ")|(" in between is crowded.
>>
>> Maybe the coding style does not describe this well enough.
BTW Supplying indent template would be great.
Please see the updated patch qemu-sparc64-tsb-asi-2.patch attached.
--
Kind regards,
Igor V. Kovalenko
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
and process termination in legacy applications. Try to guess which we want
based on the presence of multiple threads.
Also implement locking when modifying the CPU list.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.
This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
