Improve instruction name comments for easier searching
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
7ab463cb52
commit
b89e94af1d
@ -2496,7 +2496,7 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_helper_check_ieee_exceptions();
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tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
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break;
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case 0x42:
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case 0x42: /* faddd */
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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@ -2520,7 +2520,7 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_helper_check_ieee_exceptions();
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tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
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break;
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case 0x46:
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case 0x46: /* fsubd */
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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@ -2571,7 +2571,7 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_helper_check_ieee_exceptions();
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tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32);
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break;
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case 0x4e:
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case 0x4e: /* fdivd */
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gen_op_load_fpr_DT0(DFPREG(rs1));
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gen_op_load_fpr_DT1(DFPREG(rs2));
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gen_clear_float_exceptions();
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@ -3136,7 +3136,7 @@ static void disas_sparc_insn(DisasContext * dc)
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cpu_src1 = get_src1(insn, cpu_src1);
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cpu_src2 = get_src2(insn, cpu_src2);
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switch (xop & ~0x10) {
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case 0x0:
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case 0x0: /* add */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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if (xop & 0x10) {
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@ -3152,7 +3152,7 @@ static void disas_sparc_insn(DisasContext * dc)
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}
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}
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break;
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case 0x1:
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case 0x1: /* and */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_andi_tl(cpu_dst, cpu_src1, simm);
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@ -3163,7 +3163,7 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_op_logic_cc(cpu_dst);
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}
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break;
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case 0x2:
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case 0x2: /* or */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_ori_tl(cpu_dst, cpu_src1, simm);
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@ -3173,7 +3173,7 @@ static void disas_sparc_insn(DisasContext * dc)
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0x3:
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case 0x3: /* xor */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_xori_tl(cpu_dst, cpu_src1, simm);
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@ -3183,7 +3183,7 @@ static void disas_sparc_insn(DisasContext * dc)
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0x4:
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case 0x4: /* sub */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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if (xop & 0x10) {
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@ -3199,7 +3199,7 @@ static void disas_sparc_insn(DisasContext * dc)
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}
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}
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break;
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case 0x5:
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case 0x5: /* andn */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_andi_tl(cpu_dst, cpu_src1, ~simm);
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@ -3209,7 +3209,7 @@ static void disas_sparc_insn(DisasContext * dc)
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0x6:
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case 0x6: /* orn */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_ori_tl(cpu_dst, cpu_src1, ~simm);
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@ -3219,7 +3219,7 @@ static void disas_sparc_insn(DisasContext * dc)
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0x7:
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case 0x7: /* xorn */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_xori_tl(cpu_dst, cpu_src1, ~simm);
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@ -3230,7 +3230,7 @@ static void disas_sparc_insn(DisasContext * dc)
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0x8:
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case 0x8: /* addx, V9 addc */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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if (xop & 0x10)
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@ -3260,19 +3260,19 @@ static void disas_sparc_insn(DisasContext * dc)
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}
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break;
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#endif
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case 0xa:
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case 0xa: /* umul */
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CHECK_IU_FEATURE(dc, MUL);
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gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0xb:
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case 0xb: /* smul */
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CHECK_IU_FEATURE(dc, MUL);
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gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
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if (xop & 0x10)
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gen_op_logic_cc(cpu_dst);
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break;
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case 0xc:
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case 0xc: /* subx, V9 subc */
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if (IS_IMM) {
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simm = GET_FIELDs(insn, 19, 31);
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if (xop & 0x10) {
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@ -3300,13 +3300,13 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_gen_divu_i64(cpu_dst, cpu_cc_src, cpu_cc_src2);
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break;
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#endif
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case 0xe:
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case 0xe: /* udiv */
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CHECK_IU_FEATURE(dc, DIV);
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gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2);
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if (xop & 0x10)
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gen_op_div_cc(cpu_dst);
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break;
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case 0xf:
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case 0xf: /* sdiv */
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CHECK_IU_FEATURE(dc, DIV);
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gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2);
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if (xop & 0x10)
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@ -4385,19 +4385,19 @@ static void disas_sparc_insn(DisasContext * dc)
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(xop > 0x17 && xop <= 0x1d ) ||
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(xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
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switch (xop) {
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case 0x0: /* load unsigned word */
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case 0x0: /* ld, V9 lduw, load unsigned word */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x1: /* load unsigned byte */
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case 0x1: /* ldub, load unsigned byte */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x2: /* load unsigned halfword */
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case 0x2: /* lduh, load unsigned halfword */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x3: /* load double word */
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case 0x3: /* ldd, load double word */
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if (rd & 1)
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goto illegal_insn;
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else {
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@ -4417,11 +4417,11 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
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}
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break;
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case 0x9: /* load signed byte */
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case 0x9: /* ldsb, load signed byte */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0xa: /* load signed halfword */
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case 0xa: /* ldsh, load signed halfword */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
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break;
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@ -4436,7 +4436,7 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_temp_free(r_const);
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}
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break;
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case 0x0f: /* swap register with memory. Also
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case 0x0f: /* swap, swap register with memory. Also
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atomically */
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CHECK_IU_FEATURE(dc, SWAP);
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gen_movl_reg_TN(rd, cpu_val);
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@ -4446,7 +4446,7 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_gen_mov_tl(cpu_val, cpu_tmp0);
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break;
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#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
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case 0x10: /* load word alternate */
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case 0x10: /* lda, V9 lduwa, load word alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4456,7 +4456,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
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break;
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case 0x11: /* load unsigned byte alternate */
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case 0x11: /* lduba, load unsigned byte alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4466,7 +4466,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
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break;
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case 0x12: /* load unsigned halfword alternate */
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case 0x12: /* lduha, load unsigned halfword alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4476,7 +4476,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
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break;
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case 0x13: /* load double word alternate */
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case 0x13: /* ldda, load double word alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4488,7 +4488,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_ldda_asi(cpu_val, cpu_addr, insn, rd);
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goto skip_move;
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case 0x19: /* load signed byte alternate */
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case 0x19: /* ldsba, load signed byte alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4498,7 +4498,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
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break;
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case 0x1a: /* load signed halfword alternate */
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case 0x1a: /* ldsha, load signed halfword alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4518,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_ldstub_asi(cpu_val, cpu_addr, insn);
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break;
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case 0x1f: /* swap reg with alt. memory. Also
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case 0x1f: /* swapa, swap reg with alt. memory. Also
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atomically */
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CHECK_IU_FEATURE(dc, SWAP);
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#ifndef TARGET_SPARC64
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@ -4586,7 +4586,7 @@ static void disas_sparc_insn(DisasContext * dc)
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goto jmp_insn;
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save_state(dc, cpu_cond);
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switch (xop) {
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case 0x20: /* load fpreg */
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case 0x20: /* ldf, load fpreg */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_ld32u(cpu_tmp0, cpu_addr, dc->mem_idx);
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tcg_gen_trunc_tl_i32(cpu_fpr[rd], cpu_tmp0);
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@ -4605,7 +4605,7 @@ static void disas_sparc_insn(DisasContext * dc)
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}
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#endif
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break;
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case 0x22: /* load quad fpreg */
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case 0x22: /* ldqf, load quad fpreg */
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{
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TCGv_i32 r_const;
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@ -4616,7 +4616,7 @@ static void disas_sparc_insn(DisasContext * dc)
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gen_op_store_QT0_fpr(QFPREG(rd));
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}
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break;
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case 0x23: /* load double fpreg */
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case 0x23: /* lddf, load double fpreg */
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{
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TCGv_i32 r_const;
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@ -4633,19 +4633,19 @@ static void disas_sparc_insn(DisasContext * dc)
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xop == 0xe || xop == 0x1e) {
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gen_movl_reg_TN(rd, cpu_val);
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switch (xop) {
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case 0x4: /* store word */
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case 0x4: /* st, store word */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x5: /* store byte */
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case 0x5: /* stb, store byte */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x6: /* store halfword */
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case 0x6: /* sth, store halfword */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
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break;
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case 0x7: /* store double word */
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case 0x7: /* std, store double word */
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if (rd & 1)
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goto illegal_insn;
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else {
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@ -4662,7 +4662,7 @@ static void disas_sparc_insn(DisasContext * dc)
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}
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break;
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#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
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case 0x14: /* store word alternate */
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case 0x14: /* sta, V9 stwa, store word alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4672,7 +4672,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_st_asi(cpu_val, cpu_addr, insn, 4);
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break;
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case 0x15: /* store byte alternate */
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case 0x15: /* stba, store byte alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4682,7 +4682,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_st_asi(cpu_val, cpu_addr, insn, 1);
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break;
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case 0x16: /* store halfword alternate */
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case 0x16: /* stha, store halfword alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4692,7 +4692,7 @@ static void disas_sparc_insn(DisasContext * dc)
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save_state(dc, cpu_cond);
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gen_st_asi(cpu_val, cpu_addr, insn, 2);
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break;
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case 0x17: /* store double word alternate */
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case 0x17: /* stda, store double word alternate */
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#ifndef TARGET_SPARC64
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if (IS_IMM)
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goto illegal_insn;
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@ -4725,7 +4725,7 @@ static void disas_sparc_insn(DisasContext * dc)
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goto jmp_insn;
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save_state(dc, cpu_cond);
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switch (xop) {
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case 0x24: /* store fpreg */
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case 0x24: /* stf, store fpreg */
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gen_address_mask(dc, cpu_addr);
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tcg_gen_ext_i32_tl(cpu_tmp0, cpu_fpr[rd]);
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tcg_gen_qemu_st32(cpu_tmp0, cpu_addr, dc->mem_idx);
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@ -4768,7 +4768,7 @@ static void disas_sparc_insn(DisasContext * dc)
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goto nfq_insn;
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#endif
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#endif
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case 0x27: /* store double fpreg */
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case 0x27: /* stdf, store double fpreg */
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{
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TCGv_i32 r_const;
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