target-sparc: Free instruction temporaries.
Rather than creating new temporaries for constants, use the ones created in disas_sparc_insn. Remember the temps created there so that they can be freed at the end of the function. Profile data collected by TCG while booting sparc-test kernel: -avg temps/TB 70.61 max=421 +avg temps/TB 62.75 max=66 Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -49,7 +49,7 @@ static TCGv cpu_y;
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#ifndef CONFIG_USER_ONLY
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static TCGv cpu_tbr;
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#endif
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static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
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static TCGv cpu_cond, cpu_dst, cpu_addr, cpu_val;
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#ifdef TARGET_SPARC64
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static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs;
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static TCGv cpu_gsr;
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@ -1631,12 +1631,13 @@ static inline TCGv get_src1(unsigned int insn, TCGv def)
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unsigned int rs1;
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rs1 = GET_FIELD(insn, 13, 17);
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if (rs1 == 0)
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r_rs1 = tcg_const_tl(0); // XXX how to free?
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else if (rs1 < 8)
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if (rs1 == 0) {
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tcg_gen_movi_tl(def, 0);
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} else if (rs1 < 8) {
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r_rs1 = cpu_gregs[rs1];
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else
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} else {
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tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
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}
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return r_rs1;
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}
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@ -1645,20 +1646,17 @@ static inline TCGv get_src2(unsigned int insn, TCGv def)
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TCGv r_rs2 = def;
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if (IS_IMM) { /* immediate */
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target_long simm;
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simm = GET_FIELDs(insn, 19, 31);
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r_rs2 = tcg_const_tl(simm); // XXX how to free?
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target_long simm = GET_FIELDs(insn, 19, 31);
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tcg_gen_movi_tl(def, simm);
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} else { /* register */
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unsigned int rs2;
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rs2 = GET_FIELD(insn, 27, 31);
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if (rs2 == 0)
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r_rs2 = tcg_const_tl(0); // XXX how to free?
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else if (rs2 < 8)
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unsigned int rs2 = GET_FIELD(insn, 27, 31);
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if (rs2 == 0) {
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tcg_gen_movi_tl(def, 0);
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} else if (rs2 < 8) {
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r_rs2 = cpu_gregs[rs2];
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else
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} else {
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tcg_gen_ld_tl(def, cpu_regwptr, (rs2 - 8) * sizeof(target_ulong));
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}
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}
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return r_rs2;
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}
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@ -1701,6 +1699,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
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static void disas_sparc_insn(DisasContext * dc)
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{
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unsigned int insn, opc, rs1, rs2, rd;
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TCGv cpu_src1, cpu_src2, cpu_tmp1, cpu_tmp2;
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target_long simm;
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if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
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@ -1710,8 +1709,8 @@ static void disas_sparc_insn(DisasContext * dc)
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rd = GET_FIELD(insn, 2, 6);
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cpu_src1 = tcg_temp_new(); // const
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cpu_src2 = tcg_temp_new(); // const
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cpu_tmp1 = cpu_src1 = tcg_temp_new();
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cpu_tmp2 = cpu_src2 = tcg_temp_new();
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switch (opc) {
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case 0: /* branches/sethi */
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@ -4601,7 +4600,7 @@ static void disas_sparc_insn(DisasContext * dc)
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dc->npc = dc->npc + 4;
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}
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jmp_insn:
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return;
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goto egress;
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illegal_insn:
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{
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TCGv_i32 r_const;
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@ -4612,7 +4611,7 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_temp_free_i32(r_const);
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dc->is_br = 1;
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}
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return;
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goto egress;
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unimp_flush:
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{
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TCGv_i32 r_const;
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@ -4623,7 +4622,7 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_temp_free_i32(r_const);
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dc->is_br = 1;
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}
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return;
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goto egress;
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#if !defined(CONFIG_USER_ONLY)
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priv_insn:
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{
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@ -4635,19 +4634,19 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_temp_free_i32(r_const);
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dc->is_br = 1;
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}
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return;
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goto egress;
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#endif
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nfpu_insn:
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save_state(dc, cpu_cond);
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gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
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dc->is_br = 1;
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return;
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goto egress;
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#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
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nfq_insn:
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save_state(dc, cpu_cond);
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gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
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dc->is_br = 1;
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return;
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goto egress;
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#endif
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#ifndef TARGET_SPARC64
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ncp_insn:
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@ -4660,8 +4659,11 @@ static void disas_sparc_insn(DisasContext * dc)
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tcg_temp_free(r_const);
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dc->is_br = 1;
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}
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return;
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goto egress;
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#endif
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egress:
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tcg_temp_free(cpu_tmp1);
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tcg_temp_free(cpu_tmp2);
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}
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static inline void gen_intermediate_code_internal(TranslationBlock * tb,
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