Commit Graph

10247 Commits

Author SHA1 Message Date
Peter Maydell
d264871209 Migration
1 My maintainer change
 2 Jianjun's qtailq
 3 Ashijeet's only-migratable
 4 Zhanghailiang's re-active images
 5 Pankaj's change name of migration thread
 6 My PCI migration merge
 7 Juan's debug to tracing
 8 My tracing on save
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJYh59nAAoJEAUWMx68W/3nC90P/2sNW0bjFBF7mACpgylOyakM
 LwV6zYemzSPFl2MWv5MlJYOiKm6JA8azv3jbm2um518wBqVnMtJdIacBE0FGzPOu
 ZxaRdawEQbNbOB8K3nLSVhrdSvSHenSbGP6LeKb1audHT/vkFCBQt4BH30eGG8Tn
 /ugU/UpxKOJX65kTqyVc+8GCVbSfKXsp21fQgYvj7kjOwQ56/IuvnsQ8UTZrxeqZ
 My27vFv4iNdonxj6YR+GDBs5Cei2vKi9lVdXu7VzruJDMmtn3Qyros6KeDDJS6bu
 CmI4yn557zn+SfqJkckltBg27343JyYPDxP40mNvsSUY1JCWJsP47o+UnHPW3kFc
 uinuHGmz/NnB7OUS9GkYDco4eU453pvaUFSVb6STdzIHtGByZwZVOcgeP+RNFkUx
 pF8TxALaS6MfEiWO9Rn+vZEyEGBZAWaH3QXk1zd5ylXyb5W6gifHMsMYiln14FpA
 0PWrItDjt45P/1C/lS+MLsVGOQEn5xMTM2zegQOYOIQHuuW0M6xhwX5LPJPM7+XI
 6wG1iy1lxoNx5/Afm+NmzTLYSo8dEUeLq6jjUsoiU5m8tdg1QVpq2A37IWKMA7aH
 2ZvN5IX/oPDPDxt0fXzzSjRsixGfqfYHf1ghEBX0QDyVdgyTX5+MX3NKMTRVXtBX
 xTQ43oKdxYdTGmOwnhVc
 =jetb
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20170124b' into staging

Migration

1 My maintainer change
2 Jianjun's qtailq
3 Ashijeet's only-migratable
4 Zhanghailiang's re-active images
5 Pankaj's change name of migration thread
6 My PCI migration merge
7 Juan's debug to tracing
8 My tracing on save

# gpg: Signature made Tue 24 Jan 2017 18:39:35 GMT
# gpg:                using RSA key 0x0516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A  9FA9 0516 331E BC5B FDE7

* remotes/dgilbert/tags/pull-migration-20170124b:
  migration/tracing: Add tracing on save
  migration: transform remaining DPRINTF into trace_
  PCI/migration merge vmstate_pci_device and vmstate_pcie_device
  migration: Change name of live migration thread
  migration: re-active images while migration been canceled after inactive them
  migration: Fail migration blocker for --only-migratable
  migration: disallow migrate_add_blocker during migration
  migration: Allow "device add" options to only add migratable devices
  migration: Add a new option to enable only-migratable
  block/vvfat: Remove the undesirable comment
  migration: add error_report
  tests/migration: Add test for QTAILQ migration
  migration: migrate QTAILQ
  migration: extend VMStateInfo
  MAINTAINERS: Add myself as a migration submaintainer

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-24 19:25:19 +00:00
Ashijeet Acharya
fe44dc9180 migration: disallow migrate_add_blocker during migration
If a migration is already in progress and somebody attempts
to add a migration blocker, this should rightly fail.

Add an errp parameter and a retcode return value to migrate_add_blocker.

Signed-off-by: John Snow <jsnow@redhat.com>
Signed-off-by: Ashijeet Acharya <ashijeetacharya@gmail.com>
Message-Id: <1484566314-3987-5-git-send-email-ashijeetacharya@gmail.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Acked-by: Greg Kurz <groug@kaod.org>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
  Merged with recent 'Allow invtsc migration' change
2017-01-24 18:00:30 +00:00
Jianjun Duan
2c21ee769e migration: extend VMStateInfo
Current migration code cannot handle some data structures such as
QTAILQ in qemu/queue.h. Here we extend the signatures of put/get
in VMStateInfo so that customized handling is supported. put now
will return int type.

Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>

Signed-off-by: Jianjun Duan <duanj@linux.vnet.ibm.com>
Message-Id: <1484852453-12728-2-git-send-email-duanj@linux.vnet.ibm.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2017-01-24 17:54:47 +00:00
Peter Maydell
a9e404600a Two s390x fixes: One for the kvm.c build failure, and one for a bug
that might cause random guest crashes with zeroed out pages on host
 kernels with working cmma (< 4.6 and likely >= 4.10).
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYh2wiAAoJEN7Pa5PG8C+vYj4QAKfZWc6Pf42HQUfDVdgiK3cV
 8N7Ew9VHCaXO7awf9wcAgjGAX7BRPbVMB/QEpta2KmtKftxUGsfVACOAM8cZmoqj
 ItZ1bpR5/tbNMlCPEyoqkJvhyDKzL5fea0wucss224cDlV7n/AyZjei9QnzMirtZ
 rEVDbnM/BmvpGiwSmrSzXOwFTY8hOd738bm0gIVnKW8GxslChYwVrpEtrgdqL7yG
 dSRruE2h2VUC8yplre9smJk3sg5xUsIxWa4JgI3s84O++pEnB02Yi+OIqW+zG9xJ
 ABObWMls5dbqap1T2VaF3fdt/yVUuZvOl8gB3Op5m6ULSyd3m+KJdbR4XvYKpDGe
 ykJNcex+W8mlejFfo2jDLVYHK9e4PXfwtBGpogSzQj1d1+jLlAl1HhTd2v7NLQtL
 hSDTUKlRG5XmtbQ6Fm4FBDC7tdO9CmGrhSeLSZ9fJM29Hn5PMc4AERBGWEMph/ek
 j15sGUu6vqiBXAuwH17TpKrlQe8I03JqWMscvQ1mSLZSB4DwhqXl5zPqRdGATGuU
 aN/0FptfqXcBOC8/3EfK6yJXlAuCqbBbbDqqn7kN2OcYVblAUmhUgU1DkDeCRZi8
 d4d9IRBIKmVTBpO/7CPEwupLMyEGEQZcIqKpTPax7lCCgRCTAfpVRddVibKMvOa5
 aDl0EyPupUUr7/ubw4AD
 =Rmjk
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170124' into staging

Two s390x fixes: One for the kvm.c build failure, and one for a bug
that might cause random guest crashes with zeroed out pages on host
kernels with working cmma (< 4.6 and likely >= 4.10).

# gpg: Signature made Tue 24 Jan 2017 15:00:50 GMT
# gpg:                using RSA key 0xDECF6B93C6F02FAF
# gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>"
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>"
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20170124:
  s390x/kvm: fix cmma reset for KVM
  s390x/kvm: include hw_accel.h instead of kvm.h

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-24 17:26:26 +00:00
Peter Maydell
a678502e4f x86, machine, numa queue (2017-01-23)
-----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYhpFDAAoJECgHk2+YTcWma8gP/3FI1oOSw4Z2emrrMJifi7i7
 FfErjzKQX76wze8MbDIb0Biyij7/1qSz9Z4yD7+tURF49O6Qd4MpryFxgfuQx7Xo
 ahZhf+PedhBYt62RaIpFYER30mqg0JzbyLFEH/Vk8FVxOrhn2zB+MUGU6zU2Z+dE
 AAbryuruPL/sdxSDerTscnOJTxRZEs/2zIdf7aqhuqCe9P9w/lSq1mPWckBgtNJx
 V36HXm5q0nvEyBJuu3ikYD8EyQrF4nAsa+Xe0E9H2XZtA/rQX9uBasqVRS/vgS9T
 fsdHIWqJ7jS0NhkMgQJTNy/NjGEAm6xdqSHoRCqLv9qHTN1yD9C8r/N5+fOqf6jh
 wDlTVns8Se9yMrxTWt0RN3Rf64Zc2X3O1iroe596vR71AQvyXxwxN0aNEo5uPUip
 nCM6K5OJBk+vDOA93aZbKGHBWJp3gOJdAEUbgScXZvOGQa7MF+MaK8aZK6Ad9zV2
 MYxAn8RYZP/UQIzIJWeVJMC0/F/ugmdrnURltf88gqeG17x4eBw0et6PenKf779X
 vHBXok5uPMQbcV3T7HH79J4hMi2Qn8wV7G9j3CzMMT7qqYVITbq7R28FUOJIuUDm
 64jL/IXRfFDsuV72PctDkmu7UPDSioJUgsGTGTjH/6G+eUvq8utu8hWEkYnGWE4W
 thYPUaE50CCUCF6PiW6/
 =abpK
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging

x86, machine, numa queue (2017-01-23)

# gpg: Signature made Mon 23 Jan 2017 23:26:59 GMT
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-and-machine-pull-request:
  kvm: Allow invtsc migration if tsc-khz is set explicitly
  kvm: Simplify invtsc check
  hw/core/null-machine: Add the possibility to instantiate a CPU and RAM
  qemu-options: Rename variables on the -numa "cpus" option
  MAINTAINERS: Add an entry for hw/core/null-machine.c
  machine: Make possible_cpu_arch_ids() return const pointer
  pc: don't return cpu pointer from pc_new_cpu() as it's not needed anymore
  pc: cleanup: move smbios_set_cpuid() into pc_build_smbios()
  arch_init: Remove unnecessary default_config_files table
  vl: Ensure the numa_post_machine_init func in the appropriate location
  i386: Return migration-safe field on query-cpu-definitions
  i386: Remove AMD feature flag aliases from Opteron models
  x86: add AVX512_VPOPCNTDQ features

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-24 15:39:09 +00:00
Christian Borntraeger
0cf4d747cb s390x/kvm: fix cmma reset for KVM
We must reset the CMMA states for normal memory (when not on mem path),
but the current code does the opposite. This was unnoticed for some time
as the kernel since 4.6 also had a bug which mostly disabled the paging
optimizations.

Fixes: 07059effd1 ("s390x/kvm: let the CPU model control CMM(A)")
Cc: qemu-stable@nongnu.org # v2.8
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-01-24 15:47:31 +01:00
Cornelia Huck
8195d8992b s390x/kvm: include hw_accel.h instead of kvm.h
Commit b394662 ("kvm: move cpu synchronization code") switched
to hw_accel.h instead of kvm.h, but missed s390x, resulting in

  CC      s390x-softmmu/target/s390x/kvm.o
/home/cohuck/git/qemu/target/s390x/kvm.c: In function ‘kvm_sclp_service_call’:
/home/cohuck/git/qemu/target/s390x/kvm.c:1034:5: error: implicit declaration of function ‘cpu_synchronize_state’ [-Werror=implicit-function-declaration]
     cpu_synchronize_state(CPU(cpu));
     ^
/home/cohuck/git/qemu/target/s390x/kvm.c:1034:5: error: nested extern declaration of ‘cpu_synchronize_state’ [-Werror=nested-externs]
/home/cohuck/git/qemu/target/s390x/kvm.c: In function ‘sigp_initial_cpu_reset’:
/home/cohuck/git/qemu/target/s390x/kvm.c:1628:5: error: implicit declaration of function ‘cpu_synchronize_post_reset’ [-Werror=implicit-function-declaration]
     cpu_synchronize_post_reset(cs);
     ^
/home/cohuck/git/qemu/target/s390x/kvm.c:1628:5: error: nested extern declaration of ‘cpu_synchronize_post_reset’ [-Werror=nested-externs]
/home/cohuck/git/qemu/target/s390x/kvm.c: In function ‘sigp_set_prefix’:
/home/cohuck/git/qemu/target/s390x/kvm.c:1665:5: error: implicit declaration of function ‘cpu_synchronize_post_init’ [-Werror=implicit-function-declaration]
     cpu_synchronize_post_init(cs);
     ^
/home/cohuck/git/qemu/target/s390x/kvm.c:1665:5: error: nested extern declaration of ‘cpu_synchronize_post_init’ [-Werror=nested-externs]
cc1: all warnings being treated as errors
/home/cohuck/git/qemu/rules.mak:64: recipe for target 'target/s390x/kvm.o' failed

Fix this.

Fixes: b394662 ("kvm: move cpu synchronization code")
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
Acked-by: Vincent Palatin <vpalatin@chromium.org>
2017-01-24 15:45:45 +01:00
Peter Maydell
48cef39bf3 hppa-linux target support
-----BEGIN PGP SIGNATURE-----
 
 iQEcBAABAgAGBQJYhkNBAAoJEK0ScMxN0Cebf2oIAMf7xHHiG+KHKA+v/TCxwxa/
 ezVw+cqkSiR6WSV2Hr0I+0edt9CGdVInJ9mgIYTKcLFvwieWywd5JffURddqbPK5
 r0Hk0qLJLv4oKDkYv6wP37s96slnD8PGpLn292COhJwXo4oXhPtvyliRkP00Ge2/
 PQAP/9vxtiUsWNFWiGMplqfYyTYCTNG/vUkYWjpvuEZRUQ3Rb/XPdCjkAd+dFM+U
 b/jB+cwoOSXs/DTNmDmmhpmiEP6hGwYhFsNeMlPr2EK0p3AfIF+UWR2RObven1zb
 LgyXyxEsRLimSyCmbyxiuQCXsMF7Ku5TQMvb5EKTKpMZzMbqmNnaAcEbqECQCuI=
 =PyRU
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20170123' into staging

hppa-linux target support

# gpg: Signature made Mon 23 Jan 2017 17:54:09 GMT
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-hppa-20170123: (25 commits)
  target-hppa: Implement floating-point insns
  target-hppa: Implement system and memory-management insns
  target-hppa: Implement loads and stores
  target-hppa: Implement shifts and deposits
  target-hppa: Implement linux-user gateway page
  target-hppa: Implement branches
  target-hppa: Implement basic arithmetic
  target-hppa: Add nullification framework
  target-hppa: Add framework and enable compilation
  target-hppa: Add softfloat specializations
  linux-user: Add HPPA startup and main loop
  linux-user: Add HPPA signal handling
  linux-user: Add HPPA target_signal.h and target_cpu.h
  linux-user: Add HPPA target_structs.h
  linux-user: Add HPPA definitions to syscall_defs.h
  linux-user: Add HPPA target_syscall.h
  linux-user: Add HPPA termbits.h
  linux-user: Add HPPA syscall numbers
  linux-user: Add HPPA socket.h definitions
  linux-user: Add some hppa ioctls
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-24 09:52:42 +00:00
Eduardo Habkost
d99569d9d8 kvm: Allow invtsc migration if tsc-khz is set explicitly
We can safely allow a VM to be migrated with invtsc enabled if
tsc-khz is set explicitly, because:
* QEMU already refuses to start if it can't set the TSC frequency
  to the configured value.
* Management software is already required to keep device
  configuration (including CPU configuration) the same on
  migration source and destination.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170108173234.25721-3-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-23 21:26:27 -02:00
Eduardo Habkost
d74460ec1b kvm: Simplify invtsc check
Instead of searching the table we have just built, we can check
the env->features field directly.

Reviewed-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170108173234.25721-2-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-23 21:26:27 -02:00
Eduardo Habkost
bd72159db4 i386: Return migration-safe field on query-cpu-definitions
Return the migration-safe field on query-cpu-definitions. All CPU
models in x86 are migration-safe except "host".

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170116181212.31565-1-ehabkost@redhat.com>
Acked-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-23 21:25:36 -02:00
Eduardo Habkost
2a923a293d i386: Remove AMD feature flag aliases from Opteron models
When CPU vendor is set to AMD, the AMD feature alias bits on
CPUID[0x80000001].EDX are already automatically copied from CPUID[1].EDX
on x86_cpu_realizefn(). When CPU vendor is Intel, those bits are
reserved and should be zero. On either case, those bits shouldn't be set
in the CPU model table.

Commit 726a8ff686 removed those
bits from most CPU models, but the Opteron_* entries still have
them. Remove the alias bits from Opteron_* too.

Add an assert() to x86_register_cpudef_type() to ensure we don't
make the same mistake again.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20170113190057.6327-1-ehabkost@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-23 21:25:33 -02:00
He Chen
f77543772d x86: add AVX512_VPOPCNTDQ features
AVX512_VPOPCNTDQ: Vector POPCNT instructions for word and qwords.
variable precision.

Signed-off-by: He Chen <he.chen@linux.intel.com>
Message-Id: <1484272411-28073-1-git-send-email-he.chen@linux.intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-23 21:22:38 -02:00
Richard Henderson
ebe9383cae target-hppa: Implement floating-point insns
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
98a9cb792c target-hppa: Implement system and memory-management insns
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
96d6407f36 target-hppa: Implement loads and stores
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
0b1347d259 target-hppa: Implement shifts and deposits
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
7ad439df56 target-hppa: Implement linux-user gateway page
For linux, page 0 is mapped as an execute-only gateway.  A gateway
page is a special bit in the page table that allows a B,GATE insn
within that page to raise processor permissions.  This is how system
calls are implemented for HPPA.

Rather than actually map anything here, or handle permissions at all,
implement the semantics of the actual linux syscall entry points.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
98cd9ca7cc target-hppa: Implement branches
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
b2167459ae target-hppa: Implement basic arithmetic
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
129e9cc3a1 target-hppa: Add nullification framework
The HPPA cpu has a unique form of predicated execution in which
almost any instruction can set the PSW[N] (or "nullify") bit,
which suppresses execution (and even decoding) of the following
instruction.  Execution of a nullified insn clears the PSW[N] bit.

This adds a generic framework for branching over nullified insns,
or for sufficiently simple insns, transforming the writeback of
the result to a conditional move.  In the process, we want to be
able to represent PSW[N] as a TCG condition, which implies management
of the related tcg temps.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
61766fe9e2 target-hppa: Add framework and enable compilation
This is just about the minimum required to enable compilation
without actually executing any instructions.  This contains the
HPPACPU structure and the required callbacks, the gdbstub, the
basic translation loop, and a translate_one function that always
results in an illegal instruction.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Peter Maydell
598cf1c805 * QOM interface fix (Eduardo)
* RTC fixes (Gaohuai, Igor)
 * Memory leak fixes (Li Qiang, me)
 * Ctrl-a b regression (Marc-André)
 * Stubs cleanups and fixes (Leif, me)
 * hxtool tweak (me)
 * HAX support (Vincent)
 * QemuThread, exec.c and SCSI fixes (Roman, Xinhua, me)
 * PC_COMPAT_2_8 fix (Marcelo)
 * stronger bitmap assertions (Peter)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQExBAABCAAbBQJYggc9FBxwYm9uemluaUByZWRoYXQuY29tAAoJEL/70l94x66D
 5pMH/092iVHw1la8VmphQd8W7hkCHckvVbwaEJ+n4BP8MjeUNmYFJX+op9Qlpqfe
 ekYqQgK69v2UwuofVK2gqS+Y2EyFHivTESk5pS3SM3lTewV1fzCM/HVG3pTxV/ol
 V+eBnp+shrfNG3Eg7YThTqx4LkDUp24Pd3HJVblQZMVpqGzL2xUuUQzSf8F/eeQJ
 xO61pm0ovpCY5MCg3kPLx8GIkPAmcXo5jhMCTz5aLnQW6TO/mwx271a4UE2RTLZ7
 cFjNhxdGSzlnn2RwId4HVYWGU42taW6mpa8NX1hVVUXa1A2qlAfi5N/WLaH0aGYR
 J5ZTIaXdPUBx2SrUmd8udj4a818=
 =H5BQ
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* QOM interface fix (Eduardo)
* RTC fixes (Gaohuai, Igor)
* Memory leak fixes (Li Qiang, me)
* Ctrl-a b regression (Marc-André)
* Stubs cleanups and fixes (Leif, me)
* hxtool tweak (me)
* HAX support (Vincent)
* QemuThread, exec.c and SCSI fixes (Roman, Xinhua, me)
* PC_COMPAT_2_8 fix (Marcelo)
* stronger bitmap assertions (Peter)

# gpg: Signature made Fri 20 Jan 2017 12:49:01 GMT
# gpg:                using RSA key 0xBFFBD25F78C7AE83
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>"
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>"
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream: (35 commits)
  pc.h: move x-mach-use-reliable-get-clock compat entry to PC_COMPAT_2_8
  bitmap: assert that start and nr are non negative
  Revert "win32: don't run subprocess tests on Mingw32 platform"
  hax: add Darwin support
  Plumb the HAXM-based hardware acceleration support
  target/i386: Add Intel HAX files
  kvm: move cpu synchronization code
  KVM: PPC: eliminate unnecessary duplicate constants
  ramblock-notifier: new
  char: fix ctrl-a b not working
  exec: Add missing rcu_read_unlock
  x86: ioapic: fix fail migration when irqchip=split
  x86: ioapic: dump version for "info ioapic"
  x86: ioapic: add traces for ioapic
  hxtool: emit Texinfo headings as @subsection
  qemu-thread: fix qemu_thread_set_name() race in qemu_thread_create()
  serial: fix memory leak in serial exit
  scsi-block: fix direction of BYTCHK test for VERIFY commands
  pc: fix crash in rtc_set_memory() if initial cpu is marked as hotplugged
  acpi: filter based on CONFIG_ACPI_X86 rather than TARGET
  ...

# Conflicts:
#	include/hw/i386/pc.h
2017-01-20 16:42:07 +00:00
Peter Maydell
d1c82f7cc3 First set of s390x patches for 2.9:
- rework of the zpci code, giving us proper multibus support
 - introduction of the 2.9 machine
 - fixes and improvements
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJYgdReAAoJEN7Pa5PG8C+vDggP/i3eviyb2mFlnIiwazlAfBuw
 Uc6vBFDh/WWMthpzHl4PF+yujM3XbuvUN3VejdnqWLQ1PYq2p3n7rHNlR2XlBovu
 f8l2LpPZGsj1VtAr1QGBj5ipOmRs3qydXY7EDCKORbKuPeor1VW7TbeaKbfpvpZM
 rZHWMlV1UGA6kxM/B+zd9+kxBM3IYnHy3o+Gaq+cfuKyc0VRWRJmalqonjkR7EZj
 InaIyOtGonpPTlMD1GTbM71Wx/NnCugYUEX1Eq4yHX4DV15rM3B83LgTJu72txzr
 ObJmzT3XU2DKwtzo87Y6cWJ3GoxQQbwgiU6VL+l8JVtrzGfllpUdcdInQjSqxXp2
 OW8NuV6Ie02YOrczBXbBAv46PKmoLTf63hvsC4f6nNLa2O6FqxAXzYGKtOpvgOq5
 j1Q6VyzAb/vbyyW2lyMice4XJXGMxitaMGxvJG0lq/iscRpNdpz6E+dgkzO7lieF
 +ETpDsGd5miMdsAUqmIREjBCCjOzOGpC4WX0mg8Te8LmR3Rt8WYIgWuowMvbq2iG
 /qmv9a8ea2XqB+/g2ta+YqS9cPChsPJSN03Q0bo1244DMwBKuVwyXNsC9lRIkiHJ
 4b1Msoseohv9D4ghU8q6gSOU+T5nxLRT1TWBByqhkONU1C4UyKHEblop/c1oHE5k
 UZtiaQvyWFhVU4QtXeE8
 =fzmu
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20170120-v2' into staging

First set of s390x patches for 2.9:
- rework of the zpci code, giving us proper multibus support
- introduction of the 2.9 machine
- fixes and improvements

# gpg: Signature made Fri 20 Jan 2017 09:11:58 GMT
# gpg:                using RSA key 0xDECF6B93C6F02FAF
# gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>"
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>"
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20170120-v2:
  virtio-ccw: fix ring sizing
  s390x/pci: merge msix init functions
  s390x/pci: handle PCIBridge bus number
  s390x/pci: use hashtable to look up zpci via fh
  s390x/pci: PCI multibus bridge handling
  s390x/pci: optimize calling s390_get_phb()
  s390x/pci: change the device array to a list
  s390x/pci: dynamically allocate iommu
  s390x/pci: make S390PCIIOMMU inherit Object
  s390x/kvm: use kvm_gsi_routing_enabled in flic
  s390x: add compat machine for 2.9
  s390x: remove double compat statement

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-20 15:53:58 +00:00
Peter Maydell
c25bd18a04 target-arm: Enable EL2 feature bit on A53 and A57
Enable the ARM_FEATURE_EL2 bit on Cortex-A52 and
Cortex-A57, since this is all now sufficiently implemented
to work with the GICv3. We provide the usual CPU property
to disable it for backwards compatibility with the older
virt boards.

In this commit, we disable the EL2 feature on the
virt and ZynpMP boards, so there is no overall effect.
Another commit will expose a board-level property to
allow the user to enable EL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-18-git-send-email-peter.maydell@linaro.org
2017-01-20 11:15:10 +00:00
Peter Maydell
3f591a2022 target/arm/psci.c: If EL2 implemented, start CPUs in EL2
The PSCI spec states that a CPU_ON call should cause the new
CPU to be started in the highest implemented Non-secure
exception level. We were incorrectly starting it at the
exception level of the caller, which happens to be correct
if EL2 is not implemented. Implement the correct logic
as described in the PSCI 1.0 spec section 6.4:
 * if EL2 exists and SCR_EL3.HCE is set: start in EL2
 * otherwise start in EL1

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Tested-by: Andrew Jones <drjones@redhat.com>
Message-id: 1483977924-14522-17-git-send-email-peter.maydell@linaro.org
2017-01-20 11:15:10 +00:00
Peter Maydell
e45868a3f3 target-arm: Add ARMCPU fields for GIC CPU i/f config
Add fields to the ARMCPU structure to allow CPU classes to
specify the configurable aspects of their GIC CPU interface.
In particular, the virtualization support allows different
values for number of list registers, priority bits and
preemption bits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org
2017-01-20 11:15:09 +00:00
Peter Maydell
aa1b3111b3 target-arm: Expose output GPIO line for VCPU maintenance interrupt
The GICv3 support for virtualization includes an outbound
maintenance interrupt signal which is asserted when the
CPU interface wants to signal to the hypervisor that it
needs attention. Expose this as an outbound GPIO line from
the CPU object which can be wired up as a physical interrupt
line by the board code (as we do already for the CPU timers).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
2017-01-20 11:15:09 +00:00
Peter Maydell
4d2ec4da1c target/arm: Implement DBGVCR32_EL2 system register
The DBGVCR_EL2 system register is needed to run a 32-bit
EL1 guest under a Linux EL2 64-bit hypervisor. Its only
purpose is to provide AArch64 with access to the state of
the DBGVCR AArch32 register. Since we only have a dummy
DBGVCR, implement a corresponding dummy DBGVCR32_EL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-01-20 11:15:07 +00:00
Peter Maydell
87a4b27034 target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()
To run a VM in 32-bit EL1 our AArch32 interrupt handling code
needs to be able to cope with VIRQ and VFIQ exceptions.
These behave like IRQ and FIQ except that we don't need to try
to route them to Monitor mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-01-20 11:15:07 +00:00
Yi Min Zhao
a975a24aed s390x/pci: optimize calling s390_get_phb()
A function may recursively call device search functions or may call
serveral different device search function. Passing the S390pciState to
search functions as an argument instead of looking up it inside the
search functions lowers the number of calling s390_get_phb().

Signed-off-by: Yi Min Zhao <zyimin@linux.vnet.ibm.com>
Reviewed-by: Pierre Morel <pmorel@linux.vnet.ibm.com>
Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2017-01-20 10:01:59 +01:00
Vincent Palatin
6f8058238a hax: add Darwin support
Re-add the MacOSX/Darwin support:
Use the Intel HAX is kernel-based hardware acceleration module
(similar to KVM on Linux).

Based on the original "target/i386: Add Intel HAX to android emulator" patch
from David Chou <david.j.chou@intel.com> from  emu-2.2-release branch in
the external/qemu-android repository.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Message-Id: <81b85c3032da902e73e77302af508b4b1a7c0ead.1484045952.git.vpalatin@chromium.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-19 22:07:46 +01:00
Vincent Palatin
b0cb0a66d6 Plumb the HAXM-based hardware acceleration support
Use the Intel HAX is kernel-based hardware acceleration module for
Windows (similar to KVM on Linux).

Based on the "target/i386: Add Intel HAX to android emulator" patch
from David Chou <david.j.chou@intel.com>

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Message-Id: <7b9cae28a0c379ab459c7a8545c9a39762bd394f.1484045952.git.vpalatin@chromium.org>
[Drop hax_populate_ram stub. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-19 22:07:46 +01:00
Vincent Palatin
47c1c8c12f target/i386: Add Intel HAX files
That's a forward port of the core HAX interface code from the
emu-2.2-release branch in the external/qemu-android repository as used by
the Android emulator.

The original commit was "target/i386: Add Intel HAX to android emulator"
saying:
"""
  Backport of 2b3098ff27bab079caab9b46b58546b5036f5c0c
  from studio-1.4-dev into emu-master-dev

    Intel HAX (harware acceleration) will enhance android emulator performance
    in Windows and Mac OS X in the systems powered by Intel processors with
    "Intel Hardware Accelerated Execution Manager" package installed when
    user runs android emulator with Intel target.

    Signed-off-by: David Chou <david.j.chou@intel.com>
"""

It has been modified to build and run along with the current code base.
The formatting has been fixed to go through scripts/checkpatch.pl,
and the DPRINTF macros have been updated to get the instanciations checked by
the compiler.

The FPU registers saving/restoring has been updated to match the current
QEMU registers layout.

The implementation has been simplified by doing the following modifications:
- removing the code for supporting the hardware without Unrestricted Guest (UG)
  mode (including all the code to fallback on TCG emulation).
- not including the Darwin support (which is not yet debugged/tested).
- simplifying the initialization by removing the leftovers from the Android
  specific code, then trimming down the remaining logic.
- removing the unused MemoryListener callbacks.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Message-Id: <e1023837f8d0e4c470f6c4a3bf643971b2bca5be.1484045952.git.vpalatin@chromium.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-19 22:07:46 +01:00
Vincent Palatin
b39466269b kvm: move cpu synchronization code
Move the generic cpu_synchronize_ functions to the common hw_accel.h header,
in order to prepare for the addition of a second hardware accelerator.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Message-Id: <f5c3cffe8d520011df1c2e5437bb814989b48332.1484045952.git.vpalatin@chromium.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-19 22:07:46 +01:00
Paolo Bonzini
8c2b8ebf6e KVM: PPC: eliminate unnecessary duplicate constants
These are not needed since linux-headers/ provides up-to-date definitions.
The constants are in linux-headers/asm-powerpc/kvm.h.

The sole users, hw/intc/xics_kvm.c and target/ppc/kvm.c, include asm/kvm.h
via sysemu/kvm.h->linux/kvm.h.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-19 22:06:53 +01:00
Artyom Tarasenko
3390537b5d
target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs
In OpenSPARC T1+ TWINX ASIs in store instructions are aliased
with Block Initializing Store ASIs.

"UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them
in the chapter "5.9 Block Initializing Store ASIs"

Integer stores of all sizes are allowed with these ASIs.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
7285fba083
target-sparc: store the UA2005 entries in sun4u format
According to chapter 13.3 of the
UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005,
only the sun4u format is available for data-access loads.

Store UA2005 entries in the sun4u format to simplify processing.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
7dd8c0760e
target-sparc: implement UA2005 ASI_MMU (0x21)
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
d00a233443
target-sparc: add more registers to dump_mmu
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
70f44d2f4b
target-sparc: implement auto-demapping for UA2005 CPUs
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
913b5f2827
target-sparc: allow 256M sized pages
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
e5673ee45e
target-sparc: simplify ultrasparc_tsb_pointer
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
15f746cedc
target-sparc: implement UA2005 TSB Pointers
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
96df2bc99f
target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
4797a68519
target-sparc: replace the last tlb entry when no free entries left
Implement the behavior described in the chapter 13.9.11 of
UltraSPARC T1™ Supplement to the UltraSPARC Architecture 2005:

"If a TLB Data-In replacement is attempted with all TLB
entries locked and valid, the last TLB entry (entry 63) is
replaced."

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
2f1b529202
target-sparc: ignore writes to UA2005 CPU mondo queue register
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
7cd39ef234
target-sparc: allow priveleged ASIs in hyperprivileged mode
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
84f8f58766
target-sparc: use direct address translation in hyperprivileged mode
Please note that QEMU doesn't impelement Real->Physical address
translation. The "Real Address" is always the "Physical Address".

Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
5c65df364a
target-sparc: fix immediate UA2005 traps
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
f7f17ef75c
target-sparc: implement UA2005 rdhpstate and wrhpstate instructions
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
cbc3a6a4cc
target-sparc: implement UA2005 GL register
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
6e040755f1
target-sparc: implement UA2005 hypervisor traps
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
9a10756d12
target-sparc: hypervisor mode takes over nucleus mode
Accordinf to UA2005, 9.3.3 "Address Space Identifiers",

"In hyperprivileged mode, all instruction fetches and loads and stores with implicit
ASIs use a physical address, regardless of the value of TL".

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
b8e31b3cc6
target-sparc: implement UltraSPARC-T1 Strand status ASR
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
4ec3e34654
target-sparc: implement UA2005 scratchpad registers
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
e4d06ca74b
target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
1a2aefae66
target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005,
outstanding disrupting exceptions that are destined for privileged mode can only
cause a trap when the virtual processor is in nonprivileged or privileged mode and
PSTATE.ie = 1. At all other times, they are held pending.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
5b5352b2f4
target-sparc: add UltraSPARC T1 TLB #defines
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
c2c7f864df
target-sparc: add UA2005 TTE bit #defines
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
20395e6337
target-sparc: use explicit mmu register pointers
Use explicit register pointers while accessing D/I-MMU registers.
Call cpu_unassigned_access on access to missing registers.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
c9b459aab8
target-sparc: store cpu super- and hypervisor flags in TB
Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Artyom Tarasenko
1ceca92853
target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode
while IMMU/DMMU is disabled
- ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor
- signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
2017-01-18 22:03:44 +01:00
Max Filippov
3a3c9dc4ca target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-16 19:19:03 -08:00
Peter Maydell
a8c611e113 This is the same as the v3 posted except a re-base and a few extra signoffs
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJYeOOmAAoJEPvQ2wlanipE3ZUH/Rsfpl23kXCMmqoXEIhWXy+h
 yf8ARWCmpU6UKfwb+sH4vLegBfU56f62vVkGQ6oaaAbuyQ4SxCUlZGMO/rqY8/TE
 m57aM+VfEE+bIdinAtLjFM24EVp/exMfkeutK7ItzLv7GwlrBos0J5veyCuyJ15q
 pccV24jrpbJGilEeJ2GblKp3r2I3dInQGauOQhtoP3MNjHmYNSQD7noSbdN/JiTR
 9H2eV700pg3ZPaSfO+CTVQN+cHjK1FC6qLi6916YZY9llnSOnDAegBYgbwE1RIBw
 AULpWrezYveKy71eFhHVtGxnPeCJ8J4GVECMK0P0cdxzprIXFh1kZezyM4bxAGk=
 =sboI
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging

This is the same as the v3 posted except a re-base and a few extra signoffs

# gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT
# gpg:                using RSA key 0xFBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>"
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1:
  cputlb: drop flush_global flag from tlb_flush
  cpu_common_reset: wrap TCG specific code in tcg_enabled()
  qom/cpu: move tlb_flush to cpu_common_reset

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16 18:23:02 +00:00
Paolo Bonzini
d525ffabab stubs: remove stubs/kvm.c
This has a single function, just move it to the other target/*/kvm.c files.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-16 17:52:35 +01:00
Paolo Bonzini
d6da1e9eca event_notifier: cleanups around event_notifier_set_handler
Remove the useless is_external argument.  Since the iohandler
AioContext is never used for block devices, aio_disable_external
is never called on it.  This lets us remove stubs/iohandler.c.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-16 17:52:35 +01:00
Peter Maydell
2ccede18bd -----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJYeeoXAAoJEPMMOL0/L7482jcQAJFoNya2rIDrK8ljb8XldnlJ
 kvgywaceh6jZUuGTfgJ4S1k9CUvSvC3Ds9Y7qkseZ9kzktS9oIbvcuEi+INWiE6J
 ZmjP4KkYeKQ2rhiglbirHkweFmEXONqu2Ca1DfV/O6DkhyF25y1HO26Zu7P1ai2/
 oq7xNaQbot8+6fntatiRNvAcWOwrq2zHG/BHU8anaNVdgYqHViZWFOKl3oM/GF7M
 jz26SWhSduCNg4dzgULlnQsin8mnd3k9U+r2Rdo5szUhly794EOay3eVNPCmN1RF
 5tGP+pyx2m34ZiCNBxwQlcHVjNGq6vQMCrIWBo6x9wABeGStxX7HhrZQ88JtCjWU
 DQ7nbhLKaE1t39I/Ax3MCbz1c+zREHC0ivnZEMiXwdr/leP1dj6cyLw2UVQ2uk7r
 azgV6Z6AbdmCr1/kSJQQkWxTvQFzQDWTgfFXgC6LvYj+5wFp1JXphPSrGTYM72sz
 e3UnKyDHiBIK00jJ16k5wAlGI1yvu7N8zxVjAQ7WCs896ki3ita1NsG1Mgs2QAHb
 FWkinnfLZE0W7MKX9Iw3X7YUxI4r4LhODC31X7CCP/LeZPjAGV4qS96cICtm8VqM
 9/4nFFhGH15eYVKNQu/vVgjdh1IMpcmqMBtmv9Ndr5f9c/IIHlWXKGlj5qkypMpL
 14YzVoiBxP+1aUIo6mts
 =iBam
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' into staging

# gpg: Signature made Sat 14 Jan 2017 09:06:31 GMT
# gpg:                using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-2.9-pull-request:
  target-m68k: increment/decrement with SP
  target-m68k: CAS doesn't need aligned access
  target-m68k: manage pre-dec et post-inc in CAS
  target-m68k: fix gen_flush_flags()
  target-m68k: fix bit operation with immediate value
  m68k: Remove PCI and USB from config file
  target-m68k: Implement bfffo
  target-m68k: Implement bitfield ops for memory
  target-m68k: Implement bitfield ops for registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-16 12:41:35 +00:00
Max Filippov
9e03ade441 target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
4b37aaa879 target/xtensa: fix ICACHE/DCACHE options detection
Configuration overlay does not explicitly say whether there are ICACHE
and DCACHE in the core. Current code uses XCHAL_[ID]CACHE_WAYS to detect
if corresponding cache option is enabled, but that's not correct: on
cores without cache these macros are defined as 1, not as 0.
Check XCHAL_[ID]CACHE_SIZE instead.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
787eaa4904 target/xtensa: don't continue translation after exception
There's no point in continuing translating guest instructions once an
unconditional exception is thrown.
There's also no point in updating pc before any instruction is
translated, don't do it.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
d2132510ca target/xtensa: support icount
Delimit each instruction that may access timers or IRQ state with
qemu_io_start/qemu_io_end, so that qemu-system-xtensa could be run with
-icount option.

Raise EXCP_YIELD after CCOMPARE reprogramming to let tcg_cpu_exec
recalculate how long this CPU is allowed to run.

RSR now may need to terminate TB, but it can't be done in RSR handler
because the same handler is used for XSR together with WSR handler, which
may also need to terminate TB. Change RSR and WSR handlers return type
to bool indicating whether TB termination is needed (RSR) or has been
done (WSR), and add TB termination after RSR/WSR dispatcher call.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:56 -08:00
Max Filippov
59a71f7578 target/xtensa: refactor CCOUNT/CCOMPARE
Xtensa cores may have a register (CCOUNT) that counts core clock cycles.
It may also have a number of registers (CCOMPAREx); when CCOUNT value
passes the value of CCOMPAREx, timer interrupt x is raised.

Currently xtensa target counts a number of completed instructions and
assumes that for CCOUNT one instruction takes one cycle to complete.
It calls helper function to update CCOUNT register at every TB end and
raise timer interrupts. This scheme works very predictably and doesn't
have noticeable performance impact, but it is hard to use with multiple
synchronized processors, especially with coming MTTCG.

Derive CCOUNT from the virtual simulation time, QEMU_CLOCK_VIRTUAL.
Use native QEMU timers for CCOMPARE timers, one timer for each register.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:55 -08:00
Max Filippov
bd527a8323 target/xtensa: implement RUNSTALL
RUNSTALL signal stalls core execution while it's applied. It is widely
used in multicore configurations to control activity of additional
cores.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:55 -08:00
Max Filippov
17ab14acd4 target/xtensa: add static vectors selection
Xtensa cores may have two distinct addresses for the static vectors
group. Provide a function to select one of them.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2017-01-15 13:01:55 -08:00
Laurent Vivier
727d937b59 target-m68k: increment/decrement with SP
On 680x0 family only.

Address Register indirect With postincrement:

When using the stack pointer (A7) with byte size data, the register
is incremented by two.

Address Register indirect With predecrement:

When using the stack pointer (A7) with byte size data, the register
is decremented by two.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
b19578f428 target-m68k: CAS doesn't need aligned access
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-5-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
308feb9352 target-m68k: manage pre-dec et post-inc in CAS
In these cases we must update the address register after
the operation.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
695576db2d target-m68k: fix gen_flush_flags()
gen_flush_flags() is setting unconditionally cc_op_synced to 1
and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set
to something else by a previous tcg fragment.

We fix that by not setting cc_op_synced to 1
(except for gen_helper_flush_flags() that updates env->cc_op)

FIX: https://github.com/vivier/qemu-m68k/issues/19

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-3-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Laurent Vivier
fe53c2be8c target-m68k: fix bit operation with immediate value
M680x0 bit operations with an immediate value use 9 bits of the 16bit
value, while coldfire ones use only 8 bits.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1484332593-16782-2-git-send-email-laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
a45f1763cc target-m68k: Implement bfffo
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1479242669-25852-1-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
f2224f2c9a target-m68k: Implement bitfield ops for memory
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-6-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
ac815f46a3 target-m68k: Implement bitfield ops for registers
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-5-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
Richard Henderson
86c9ab2776 target/arm: Fix ubfx et al for aarch64
The patch in 59a71b4c5b suffered from a merge failure
when compared to the original patch in

  http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.html

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-13 09:48:20 -08:00
Peter Maydell
b6af8ea602 x86 and machine queue, 2017-01-17
Includes i386, CPU, NUMA, and memory backends changes.
 
 i386:
  target/i386: Fix bad patch application to translate.c
 
 CPU:
  qmp: Report QOM type name on query-cpu-definitions
 
 NUMA:
  numa: make -numa parser dynamically allocate CPUs masks
 
 Memory backends:
  qom: remove unused header
  monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
  monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJYd8KHAAoJECgHk2+YTcWmHL4QALOeGD9hts4xw+1Q/kIzZYKt
 4fDdhGxyZ5faOiSUL8F2bOMXcOCsH+oNgvapxyKsZw1z79VbdEHgSUJtgv89Dz58
 sZ6UA1YAg2cWVaKFbRm98qGOImHmPEyNS/C7EpkejB41TXWAXM6Oh4PYeYgaibi3
 HxHW+oi7/4ugAs0dnIihaE/kMQmO4qWTtuDGosTPkTl4XuwWeMbC2BXaYIyZKAS5
 F2MgEXbxph889PcsNMeE5xy5hw3CA34gpq+Xs+ai+Box7AjIGemZVgqHdYcSjMSI
 pmaLO8R1ciyzPfjgwojOkVzFIft1A5XyoAiWUTmR0o3KQLs0gmG7XkKpjId2UzTk
 Xl2mxQjWAxZNlbfOoNYRf6UhwAIjpKYrjYyr0nrrumXB+9YH1d/0ix+3UjtZLU+e
 Qgg+sSgv11MPpdc9t1gcvXVzB+h+eqp7WLYH3j5vdYJZwLVVJJusXJxmyy72BrdK
 2AdL14RziPYvVvlQZ4fM5wp1HtTMUe96VLhHxwOpBDcdcdZIk1E8SxZXde1fUk41
 OS+egry27xgoJ6pJMZlB8t4TKqcSj8x5dNLi9+qjtfDSRonPAROCBus4jugUd6Ds
 xeW06s7Hbm0BxGYn/3s860RPTJrJPX3+MjLtFbIdXSbwHWM6jsy4U9qQdLRlneR9
 oTCyWo0AeuDFe0bQ110m
 =KII3
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging

x86 and machine queue, 2017-01-17

Includes i386, CPU, NUMA, and memory backends changes.

i386:
 target/i386: Fix bad patch application to translate.c

CPU:
 qmp: Report QOM type name on query-cpu-definitions

NUMA:
 numa: make -numa parser dynamically allocate CPUs masks

Memory backends:
 qom: remove unused header
 monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
 monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends

# gpg: Signature made Thu 12 Jan 2017 17:53:11 GMT
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-and-machine-pull-request:
  qmp: Report QOM type name on query-cpu-definitions
  numa: make -numa parser dynamically allocate CPUs masks
  target/i386: Fix bad patch application to translate.c
  monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends
  monitor: reuse user_creatable_add_opts() instead of user_creatable_add()
  qom: remove unused header

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-13 14:38:21 +00:00
Alex Bennée
d10eb08f5d cputlb: drop flush_global flag from tlb_flush
We have never has the concept of global TLB entries which would avoid
the flush so we never actually use this flag. Drop it and make clear
that tlb_flush is the sledge-hammer it has always been.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[DG: ppc portions]
Acked-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-13 14:24:37 +00:00
Alex Bennée
1f5c00cfdb qom/cpu: move tlb_flush to cpu_common_reset
It is a common thing amongst the various cpu reset functions want to
flush the SoftMMU's TLB entries. This is done either by calling
tlb_flush directly or by way of a general memset of the CPU
structure (sometimes both).

This moves the tlb_flush call to the common reset function and
additionally ensures it is only done for the CONFIG_SOFTMMU case and
when tcg is enabled.

In some target cases we add an empty end_of_reset_fields structure to the
target vCPU structure so have a clear end point for any memset which
is resetting value in the structure before CPU_COMMON (where the TLB
structures are).

While this is a nice clean-up in general it is also a precursor for
changes coming to cputlb for MTTCG where the clearing of entries
can't be done arbitrarily across vCPUs. Currently the cpu_reset
function is usually called from the context of another vCPU as the
architectural power up sequence is run. By using the cputlb API
functions we can ensure the right behaviour in the future.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-13 14:24:31 +00:00
Peter Maydell
b6c08970bc TriCore FPU patches
-----BEGIN PGP SIGNATURE-----
 
 iQJTBAABCgA9FiEEbmNqfoPy3Qz6bm43CtLGOWtpyhQFAlh2NbsfHGtiYXN0aWFu
 QG1haWwudW5pLXBhZGVyYm9ybi5kZQAKCRAK0sY5a2nKFLuOEAC5twyd1sXr1lGZ
 NNY/QwxBteNiEFhzl4FtvOCiIUF5V/FEo7h1Bz1AHsGqaUWMKFdTtFO1dT8VWyl+
 wQb0hnOtOiUxEl/UU35cviGzxr5iNWWUx/+yQezUrx7z8HBXUHpWgMbRvJSQ7ZpK
 Jjp/7zwbwtWjALTUPNOZZPWi7yYGSOXPIBHfSvsRx1KKC4o6hpQndm9uXOHUojf4
 DPrGXWayieRQCmJOSeEOosVjU/e4bNOIdQU2/P3fV9MRPzqapG0U7NsVZfcqxiUY
 loEUKOe7jhNrVnwSqStCpdQlA2W1h0PoaXLc3kEw7D92S+rHk6pCDsHlq19bJvIV
 /KrymUmbbw5D5W/GNEtyXY6Q+x7hK+zQ2pvoPfG/NVXHBdEp1lT/qrKJQQJqfmLi
 j2qozmty1aBrYMYL34caeXoFILJVUxwiZ51DKN3Y/MOArPV/ehPUujKfIRksCRJd
 nu+kUur9aRR4tmb8XwjEVj2ewtJhOE6SUdxRUT/C+kAGUAzRqQcPgTMhcj8UvITl
 lyrMB69zh3s3U1FthGefLuy+7XSy/tg+slqeFmHpt6tlU6+eD//jk/m+ryC236jq
 fqUIXYrKZM9hG4/q6OsdM5HN2uVPKGtZTJUxkGl6uLeRZHrjLoeMQJ5VM624/mJx
 6guBOiHSf4t+IgHuOumjTeIz5QaGuw==
 =80tR
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2' into staging

TriCore FPU patches

# gpg: Signature made Wed 11 Jan 2017 13:40:11 GMT
# gpg:                using RSA key 0x0AD2C6396B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E  6E37 0AD2 C639 6B69 CA14

* remotes/bkoppelmann/tags/pull-tricore-2017-01-11-2:
  target-tricore: Add updfl instruction
  target-tricore: Added new JNE instruction variant
  target-tricore: Added new MOV instruction variant
  target-tricore: Added MADD.F and MSUB.F instructions
  target-tricore: Added FTOUZ instruction

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-12 18:29:49 +00:00
Eduardo Habkost
8ed877b784 qmp: Report QOM type name on query-cpu-definitions
The new typename attribute on query-cpu-definitions will be used
to help management software use device-list-properties to check
which properties can be set using -cpu or -global for the CPU
model.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <1479320499-29818-1-git-send-email-ehabkost@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-12 15:51:36 -02:00
Doug Evans
410e98146f target/i386: Fix bad patch application to translate.c
In commit c52ab08aee,
the patch snippet for the "syscall" insn got applied to "iret".

Signed-off-by: Doug Evans <dje@google.com>
Message-Id: <f403045cde4049058c05446d5c04@google.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-12 15:51:35 -02:00
Bastian Koppelmann
50788a3fdb target-tricore: Add updfl instruction
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11 14:37:37 +01:00
Peer Adelt
dedd8c9c32 target-tricore: Added new JNE instruction variant
If D[15] is != sign_ext(const4) then PC will be set to (PC +
zero_ext(disp4 + 16)).

[BK: fixed style errors]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2017-01-11 14:37:28 +01:00
Peer Adelt
550929dd46 target-tricore: Added new MOV instruction variant
Puts the content of data register D[a] into E[c][63:32] and the
content of data register D[b] into E[c][31:0].

[BK: fix style error]
[BK: Allocate temporaries only when needed]
Signed-off-by: Peer Adelt <peer.adelt@c-lab.de>
Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2017-01-11 14:37:15 +01:00
Bastian Koppelmann
ddd7fead8c target-tricore: Added MADD.F and MSUB.F instructions
Multiplies D[a] and D[b] and adds/subtracts the result to/from D[d].
The result is put in D[c]. All operands are floating-point numbers.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11 14:37:07 +01:00
Bastian Koppelmann
8f75983db8 target-tricore: Added FTOUZ instruction
Converts a 32-bit floating point number to an unsigned int. The
result is rounded towards zero.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-01-11 14:36:51 +01:00
Richard Henderson
4885c3c495 target-i386: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:49:59 -08:00
Richard Henderson
3253cddd21 target-tilegx: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:49:59 -08:00
Richard Henderson
08da3180dc target-sparc: Use ctpop helper
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:49:55 -08:00
Richard Henderson
250a87d556 target-s390x: Avoid a loop for popcnt
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:48:57 -08:00
Richard Henderson
7977000220 target-ppc: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:48:57 -08:00
Richard Henderson
de26a584d2 target-alpha: Use ctpop helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:48:56 -08:00
Richard Henderson
3946c6aa3d target-xtensa: Use clrsb helper
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:47:48 -08:00
Richard Henderson
16256947eb target-tricore: Use clrsb helper
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:47:48 -08:00
Richard Henderson
bc21dbcc12 target-arm: Use clrsb helper
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:47:48 -08:00
Richard Henderson
e5143c9088 target-i386: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
7539a012f6 target-arm: Use clz opcode
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
b79ea941d6 target-xtensa: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
03a733dc62 target-unicore32: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
0efa820854 target-tricore: Use clz opcode
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
c3aa369e5d target-tilegx: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
0f9712b117 target-s390x: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
9b8514e56e target-ppc: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
555baef8d0 target-openrisc: Use clz and ctz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
1a0196c5c7 target-mips: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
5318420c62 target-microblaze: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
272694a29d target-cris: Use clz opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
881549da4b target-alpha: Use the ctz and clz opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:11 -08:00
Richard Henderson
f6156b8fb0 target-s390x: Use the new deposit and extract ops
Use the new primitives for RISBG.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
7b4d326f47 target-ppc: Use the new deposit and extract ops
Use the new primitives for RDWINM and RLDICL.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
6eebb7a438 target-mips: Use the new extract op
Use extract for EXT and DEXT.

Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
04fc2f1c8f target-i386: Use new deposit and extract ops
A couple of places where it was easy to identify a right-shift
followed by an extract or and-with-immediate, and the obvious
sign-extract from a high byte register.

Acked-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
59a71b4c5b target-arm: Use new deposit and extract ops
Use the new primitives for UBFX and SBFX.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Richard Henderson
f49f1ae73b target-alpha: Use deposit and extract ops
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10 08:06:10 -08:00
Peter Maydell
dbe2b65566 -----BEGIN PGP SIGNATURE-----
iQIcBAABAgAGBQJYYqpMAAoJEPMMOL0/L748XoIP/i+Nwb3SjQWJG4J8dJgIBxuO
 rNYkehTVS+VcPXf0m/swA7Il4TFQhbgHjxapqMDneeoV6G7MMRTElZ91ws5a9YbP
 9d4WlJh1LBbr7uBcXHpBpQOaZaL9ng0P07erXznGQ6NWsZ0IpEj+6rxMHEFAtWDn
 J44+6Ea7dMCyZFI0ASJXIm7FA24sBwK/AK1VTFeRq0TU66zFD7AfVBiMuW9J1oFU
 kiwSw7jQalfpypUA3vcSv8KCh/itxoxaz1ZUKkeOfraqCgMf3Vte6eqMxcVd2+0y
 OYSPpQo6jCXHNf+NIC2edpFUf+loEybdhtidqNoxLaunC+XmYXuApu+FAD1ZjPvU
 gghqpObEzqcrIxtPkIKDI54iwfBJSWRkIDlUWFspwiegvdO05Inf9+3yADLBCKQm
 x53iGUhNII1RGnADhEV7XCakfQjsEDtWMBF0v6Ty4BGyZfiB5BHxkBMDU6N8FtFx
 8VYAfU/kDA1Mz6l65AuU9fwEGrBOI8g7pISLRhCVRdouBH6IDoonKm/5qkNwpxnl
 UsL2bJ2v38ABcI0v5TGgGpuLWQVxw5OcByMGUsq5lBwyojAZhCiyKuMp0DYrtdD/
 SN6rSpSRer47zWyyj1RYsbwdPVSqGueZbKD/oXCxAuWWdLqCa4MoqddrG2EqFdMy
 UeZpjr4O4Mf3RsY7nRSs
 =vYbn
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' into staging

# gpg: Signature made Tue 27 Dec 2016 17:52:12 GMT
# gpg:                using RSA key 0xF30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier/tags/m68k-for-2.9-pull-request:
  target-m68k: free TCG variables that are not
  target-m68k: add rol/ror/roxl/roxr instructions
  target-m68k: Inline shifts
  target-m68k: Do not cpu_abort on undefined insns
  target-m68k: Implement 680x0 movem
  target-m68k: add cas/cas2 ops
  target-m68k: add abcd/sbcd/nbcd
  target-m68k: add 680x0 divu/divs variants
  target-m68k: add 64bit mull
  target-m68k: add cmpm
  target-m68k: Split gen_lea and gen_ea
  target-m68k: Delay autoinc writeback

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-28 17:11:11 +00:00
Laurent Vivier
2b5e217067 target-m68k: free TCG variables that are not
This is a cleanup patch. It adds call to tcg_temp_free()
when it is missing.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27 18:28:40 +01:00
Laurent Vivier
0194cf31cf target-m68k: add rol/ror/roxl/roxr instructions
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27 18:28:40 +01:00
Richard Henderson
367790cce8 target-m68k: Inline shifts
Also manage word and byte operands and fix the computation of
overflow in the case of M68000 arithmetic shifts.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-4-git-send-email-rth@twiddle.net>
2016-12-27 18:28:40 +01:00
Richard Henderson
72d2e4b6a4 target-m68k: Do not cpu_abort on undefined insns
Report this properly via exception and, importantly, allow
the disassembler the chance to tell us what insn is not handled.

Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-3-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-12-27 18:28:40 +01:00
Laurent Vivier
7b542eb96d target-m68k: Implement 680x0 movem
680x0 movem can load/store words and long words and can use more
addressing modes.  Coldfire can only use long words with (Ax) and
(d16,Ax) addressing modes.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-2-git-send-email-rth@twiddle.net>
2016-12-27 18:28:39 +01:00
Laurent Vivier
14f944063a target-m68k: add cas/cas2 ops
Implement CAS using cmpxchg.
Implement CAS2 using helper and either cmpxchg when
the 32bit addresses are consecutive, or with
parallel_cpus+cpu_loop_exit_atomic() otherwise.

Suggested-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27 18:21:09 +01:00
Laurent Vivier
fb5543d820 target-m68k: add abcd/sbcd/nbcd
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27 18:16:42 +01:00
Laurent Vivier
0ccb9c1d81 target-m68k: add 680x0 divu/divs variants
Update helper to set the throwing location in case of div-by-0.
Cleanup divX.w and add quad word variants of divX.l.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twidle.net>
[laurent: modified to clear Z on overflow, as found with risu]
2016-12-27 18:16:42 +01:00
Laurent Vivier
8be95defd6 target-m68k: add 64bit mull
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twidle.net>
2016-12-27 18:16:42 +01:00
Laurent Vivier
817af1c72d target-m68k: add cmpm
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1477604609-2206-2-git-send-email-laurent@vivier.eu>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478206203-4606-4-git-send-email-rth@twiddle.net>
2016-12-27 18:16:42 +01:00
Richard Henderson
f84aab269d target-m68k: Split gen_lea and gen_ea
Provide gen_lea_mode and gen_ea_mode, where the mode can be
specified manually, rather than taken from the instruction.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478206203-4606-3-git-send-email-rth@twiddle.net>
2016-12-27 18:16:42 +01:00
Richard Henderson
8a1e52b69d target-m68k: Delay autoinc writeback
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478206203-4606-2-git-send-email-rth@twiddle.net>
2016-12-27 18:16:42 +01:00
Cédric Le Goater
91db4642f8 target-arm: Add VBAR support to ARM1176 CPUs
ARM1176 CPUs have TrustZone support and can use the Vector Base
Address Register, but currently, qemu only adds VBAR support to ARMv7
CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used
for ARMv7 and ARM1176 CPUs.

The VBAR feature is always set for ARMv7 because some legacy boards
require it even if this is not architecturally correct.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 1481810970-9692-1-git-send-email-clg@kaod.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27 14:59:30 +00:00
Peter Maydell
c9b61d9aa1 target-arm: Log AArch64 exception returns
We already log exception entry; add logging of the AArch64 exception
return path as well.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27 14:59:25 +00:00
Richard Henderson
0a97c40f8e target-arm: Fix aarch64 disas_ldst_single_struct
We add s->be_data within do_vec_ld/st.  Adding it here means that
we have the wrong bits set in SIZE for a big-endian host, leading
to g_assert_not_reached in write_vec_element and read_vec_element.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1481085020-2614-3-git-send-email-rth@twiddle.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27 14:59:24 +00:00
Richard Henderson
416d72b97b target-arm: Fix aarch64 vec_reg_offset
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used
for a big-endian host doesn't do what's intended.  Fix this by adding
in the vfp.regs offset after computing the inter-register offset.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27 14:59:24 +00:00
Julian Brown
0f1944735b Correct value of ARM Cortex-A8 MVFR1 register.
The value of the MVFR1 (Media and VFP Feature Register 1) register for
the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K),
with the "full denormal arithmetic" and "propagation of NaN" fields
holding both 0 instead of both 1.

I had a go tracing the history of the use of this value, and it seems
it's always just been wrong in QEMU: maybe it was derived from early
documentation, or guessed based on the use of a "VFP Lite" implementation
in the Cortex-A8.

Depending on the startup/early-boot code in use, this can manifest as
failure to perform denormal arithmetic properly: in our case, selecting
a Cortex-A8 CPU when using QEMU as an instruction-set simulator for
bare-metal GCC testing caused tests using denormal arithmetic to
fail. Problems might be masked (or not occur) when using a full OS kernel
with suitable trap handlers (I'm not sure).

Signed-off-by: Julian Brown <julian@codesourcery.com>
Message-id: 1481130858-31767-1-git-send-email-julian@codesourcery.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27 14:59:23 +00:00
Kirill A. Shutemov
6c7c3c21f9 x86: implement la57 paging mode
The new paging more is extension of IA32e mode with more additional page
table level.

It brings support of 57-bit vitrual address space (128PB) and 52-bit
physical address space (4PB).

The structure of new page table level is identical to pml4.

The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16].

CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level
paging mode.

Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com>
[Drop changes to target-i386/translate.c. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22 16:01:04 +01:00
Doug Evans
c52ab08aee target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns
The syscall and sysret instructions behave a bit differently:
TF is checked after the instruction completes.
This allows the o/s to disable #DB at a syscall by adding TF to FMASK.
And then when the sysret is executed the #DB is taken "as if" the
syscall insn just completed.

Signed-off-by: Doug Evans <dje@google.com>
Message-Id: <94eb2c0bfa1c6a9fec0543057483@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22 16:01:04 +01:00
Marcelo Tosatti
6053a86fe7 kvmclock: reduce kvmclock difference on migration
Check for KVM_CAP_ADJUST_CLOCK capability KVM_CLOCK_TSC_STABLE, which
indicates that KVM_GET_CLOCK returns a value as seen by the guest at
that moment.

For new machine types, use this value rather than reading
from guest memory.

This reduces kvmclock difference on migration from 5s to 0.1s
(when max_downtime == 5s).

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Message-Id: <20161121105052.598267440@redhat.com>
[Add comment explaining what is going on. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22 16:00:56 +01:00
Doug Evans
e3592bc9d8 x86: Fix x86_64 'g' packet response to gdb from 32-bit mode.
The remote protocol can't handle flipping back and forth
between 32-bit and 64-bit regs. To compensate, pretend "as if"
on 64-bit cpu when in 32-bit mode.

Signed-off-by: Doug Evans <dje@google.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-Id: <001a113dca8274572005406e03c3@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22 16:00:25 +01:00
Yi Sun
638cbd452d target-i386: Add Intel SHA_NI instruction support.
Add SHA_NI feature bit. Its spec can be found at:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf

Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Message-Id: <1481683803-10051-1-git-send-email-yi.y.sun@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22 16:00:25 +01:00
Thomas Huth
fcf5ef2ab5 Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-12-20 21:52:12 +01:00