target-i386: Use new deposit and extract ops
A couple of places where it was easy to identify a right-shift followed by an extract or and-with-immediate, and the obvious sign-extract from a high byte register. Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -383,8 +383,7 @@ static void gen_op_mov_reg_v(TCGMemOp ot, int reg, TCGv t0)
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static inline void gen_op_mov_v_reg(TCGMemOp ot, TCGv t0, int reg)
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{
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if (ot == MO_8 && byte_reg_is_xH(reg)) {
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tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
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tcg_gen_ext8u_tl(t0, t0);
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tcg_gen_extract_tl(t0, cpu_regs[reg - 4], 8, 8);
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} else {
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tcg_gen_mov_tl(t0, cpu_regs[reg]);
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}
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@ -3768,8 +3767,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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/* Extract the LEN into a mask. Lengths larger than
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operand size get all ones. */
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tcg_gen_shri_tl(cpu_A0, cpu_regs[s->vex_v], 8);
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tcg_gen_ext8u_tl(cpu_A0, cpu_A0);
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tcg_gen_extract_tl(cpu_A0, cpu_regs[s->vex_v], 8, 8);
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tcg_gen_movcond_tl(TCG_COND_LEU, cpu_A0, cpu_A0, bound,
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cpu_A0, bound);
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tcg_temp_free(bound);
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@ -3920,9 +3918,8 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
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gen_compute_eflags(s);
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}
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carry_in = cpu_tmp0;
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tcg_gen_shri_tl(carry_in, cpu_cc_src,
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ctz32(b == 0x1f6 ? CC_C : CC_O));
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tcg_gen_andi_tl(carry_in, carry_in, 1);
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tcg_gen_extract_tl(carry_in, cpu_cc_src,
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ctz32(b == 0x1f6 ? CC_C : CC_O), 1);
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}
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switch (ot) {
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@ -5447,21 +5444,25 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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rm = (modrm & 7) | REX_B(s);
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if (mod == 3) {
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gen_op_mov_v_reg(ot, cpu_T0, rm);
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switch (s_ot) {
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case MO_UB:
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tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
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break;
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case MO_SB:
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tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
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break;
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case MO_UW:
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tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
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break;
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default:
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case MO_SW:
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tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
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break;
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if (s_ot == MO_SB && byte_reg_is_xH(rm)) {
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tcg_gen_sextract_tl(cpu_T0, cpu_regs[rm - 4], 8, 8);
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} else {
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gen_op_mov_v_reg(ot, cpu_T0, rm);
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switch (s_ot) {
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case MO_UB:
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tcg_gen_ext8u_tl(cpu_T0, cpu_T0);
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break;
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case MO_SB:
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tcg_gen_ext8s_tl(cpu_T0, cpu_T0);
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break;
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case MO_UW:
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tcg_gen_ext16u_tl(cpu_T0, cpu_T0);
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break;
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default:
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case MO_SW:
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tcg_gen_ext16s_tl(cpu_T0, cpu_T0);
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break;
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}
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}
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gen_op_mov_reg_v(d_ot, reg, cpu_T0);
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} else {
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