Peer Adelt dedd8c9c32 target-tricore: Added new JNE instruction variant ... If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt <peer.adelt@c-lab.de> Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>		2017-01-11 14:37:28 +01:00
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alpha
arm	target-arm: Add VBAR support to ARM1176 CPUs	2016-12-27 14:59:30 +00:00
cris
i386	x86: implement la57 paging mode	2016-12-22 16:01:04 +01:00
lm32
m68k	target-m68k: free TCG variables that are not	2016-12-27 18:28:40 +01:00
microblaze
mips
moxie
openrisc
ppc
s390x
sh4
sparc
tilegx
tricore	target-tricore: Added new JNE instruction variant	2017-01-11 14:37:28 +01:00
unicore32
xtensa