qemu/target
Richard Henderson ac815f46a3 target-m68k: Implement bitfield ops for registers
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <1478699171-10637-5-git-send-email-rth@twiddle.net>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14 10:06:21 +01:00
..
alpha target-alpha: Use ctpop helper 2017-01-10 08:48:56 -08:00
arm x86 and machine queue, 2017-01-17 2017-01-13 14:38:21 +00:00
cris target-cris: Use clz opcode 2017-01-10 08:06:11 -08:00
i386 x86 and machine queue, 2017-01-17 2017-01-13 14:38:21 +00:00
lm32
m68k target-m68k: Implement bitfield ops for registers 2017-01-14 10:06:21 +01:00
microblaze target-microblaze: Use clz opcode 2017-01-10 08:06:11 -08:00
mips target-mips: Use clz opcode 2017-01-10 08:06:11 -08:00
moxie
openrisc target-openrisc: Use clz and ctz opcodes 2017-01-10 08:06:11 -08:00
ppc x86 and machine queue, 2017-01-17 2017-01-13 14:38:21 +00:00
s390x x86 and machine queue, 2017-01-17 2017-01-13 14:38:21 +00:00
sh4
sparc target-sparc: Use ctpop helper 2017-01-10 08:49:55 -08:00
tilegx target-tilegx: Use ctpop helper 2017-01-10 08:49:59 -08:00
tricore TriCore FPU patches 2017-01-12 18:29:49 +00:00
unicore32 target-unicore32: Use clz opcode 2017-01-10 08:06:11 -08:00
xtensa target-xtensa: Use clrsb helper 2017-01-10 08:47:48 -08:00