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4d2ec4da1c
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Peter Maydell 4d2ec4da1c target/arm: Implement DBGVCR32_EL2 system register 
The DBGVCR_EL2 system register is needed to run a 32-bit
EL1 guest under a Linux EL2 64-bit hypervisor. Its only
purpose is to provide AArch64 with access to the state of
the DBGVCR AArch32 register. Since we only have a dummy
DBGVCR, implement a corresponding dummy DBGVCR32_EL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-01-20 11:15:07 +00:00
..
alpha cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
arm target/arm: Implement DBGVCR32_EL2 system register 2017-01-20 11:15:07 +00:00
cris qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
i386 This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
lm32 qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
m68k This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
microblaze cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
mips cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
moxie qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
openrisc cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
ppc This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
s390x This is the same as the v3 posted except a re-base and a few extra signoffs 2017-01-16 18:23:02 +00:00
sh4 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
sparc target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs 2017-01-18 22:03:44 +01:00
tilegx qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
tricore qom/cpu: move tlb_flush to cpu_common_reset 2017-01-13 14:24:31 +00:00
unicore32 cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00
xtensa cputlb: drop flush_global flag from tlb_flush 2017-01-13 14:24:37 +00:00