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516 Commits

Author SHA1 Message Date
Stanislav Shwartsman
f3730cd784 Implemented two last SSE instructions RSQRTSS and RSQRTPS 
MSDEV workspaces updated with new file
CPUID will detect and CPU will execute FXSAVE/FXRSTOR instructions when cpu-level-hacked=6 and not only when cpu-level=6
 2003-12-31 17:35:43 +00:00
Stanislav Shwartsman
2dae51fc3f Fixed compilation error 2003-12-30 23:14:47 +00:00
Stanislav Shwartsman
52d75d7aed Fast table-based implementation of reciprocal (RCPSS/RCPPS) 
This implemntation is much more clear than old one.
RSQRTSS/RSQRTPS coming soon.
 2003-12-30 23:06:59 +00:00
Christophe Bothamy
e7e0b40bd1 - remove calculation on cr3 in dtranslate_linear, one of the most called functions (patch by Conn Clark) 2003-12-30 22:12:45 +00:00
Christophe Bothamy
e3bec02532 - fix bug preventing x86-64 detection 2003-12-30 14:14:28 +00:00
Stanislav Shwartsman
6fe8e9260b remove redundant CPU LEVEL checks for x86-64 2003-12-29 21:47:36 +00:00
Daniel Gimpelevich
fb80d47dbf *** empty log message *** 2003-12-29 21:24:35 +00:00
Stanislav Shwartsman
be9c0aeeec Enable FXSAVE/FXRESTOR instructions for BX_HACKED_CPU_LEVEL=6 also 2003-12-29 21:23:46 +00:00
Stanislav Shwartsman
b770d809d3 Clearify disagnostic messages. 
Remove redundant cpu level checks for x86-64
 2003-12-29 21:20:58 +00:00
Stanislav Shwartsman
7deb9491da Fixed compilation error for FPU disabled case 2003-12-29 20:26:05 +00:00
Daniel Gimpelevich
68fd1dc95b cleanup optimizations & fix compile error 2003-12-29 07:28:28 +00:00
Stanislav Shwartsman
fd60a984a0 Instructions that should not check pending FPU exceptions 2003-12-28 18:58:15 +00:00
Stanislav Shwartsman
0eb71999db Added missed 287 opcodes which should be executed as NOP in 387+ 2003-12-28 18:19:41 +00:00
Stanislav Shwartsman
9ccb363ec3 bochs style decode/execute of FPU instructions. 
With this coding style each instruction could be implemented separatelly even not together with current Bochs FPU emulator.
Step-by-step I am going to transfer all FPU instructions from current Bochs FPU emulator to new style and remove an old bugged emulator.
Anyway, now I could implement all currently missed FPU instructions without hacking wm-fpu-emu.
 2003-12-27 13:50:06 +00:00
Stanislav Shwartsman
ab6b9c7dcb New table-based disassembler: 
* Fully supports
	* MMX/XMM/3DNOW instruction sets
	* FPU instruction
	* SSE3 extensions
 currently only 16/32 bit mode bug anyway, it is much better that old one ;)
 2003-12-24 20:32:59 +00:00
Daniel Gimpelevich
fff74a6f83 Fixed incompatibility with gcc3.3, I think. 2003-11-28 15:07:29 +00:00
Zwane Mwaikambo
b152c966fc remove 'const' from bx_local_apic_c::get_type declaration, fix for wrong 
class member being called in bx_generic_apic_c::deliver
 2003-11-23 02:44:15 +00:00
Zwane Mwaikambo
8ca600665e Fix 3DNow compilation 2003-11-22 22:39:55 +00:00
Stanislav Shwartsman
b17671f5ef Fixed compilation error 2003-11-19 20:57:13 +00:00
Stanislav Shwartsman
a6c1bdbbb2 Optimization of RCPSS/RCPPS functions 2003-11-19 20:27:58 +00:00
Stanislav Shwartsman
cdb68ff8c8 Reverting back the changes in data_xfer16.cc 
Add/Fix bx_info messages in proc_ctrl.cc
 2003-11-13 21:57:13 +00:00
Stanislav Shwartsman
d51aece0c1 Change BX_PANIC messages to BX_INFO when behaviour is accepted with Intel/AMD docs. 
Instructions MOV_CxRx and MOV_RxCx are not supported in v8086 mode according to Intel manuals.
Also these instructions are treated as register-to-register regardless to MODRM byte fields (according to AMD manuals)
Also commit fix for MOV_EwSw by Kevin
 2003-11-13 21:17:31 +00:00
Stanislav Shwartsman
ac50ab3760 Implemented RCPSS/RCPPS SSE instructions 2003-11-07 20:53:27 +00:00
Stanislav Shwartsman
2f20c087c3 Remove code duplication from FXRSTOR functioN 2003-10-25 10:32:54 +00:00
Stanislav Shwartsman
4e74efdf0c Fast fxsave/fxrstor 2003-10-24 20:44:43 +00:00
Stanislav Shwartsman
ac739aa8b7 Fixed possible compilation problem 2003-10-24 20:06:12 +00:00
Stanislav Shwartsman
ac20b6405a - FXSAVE/FXRSTOR instructions should be available in P6 mode 
- Added second UD2 opcode to fetchdecode
- Added RDPMC instruction to fetchdecode
- 'changes' updated
 2003-10-24 18:34:16 +00:00
Stanislav Shwartsman
d5210af668 Two new bx_instrumentation callbacks 2003-10-09 19:05:13 +00:00
Stanislav Shwartsman
e57662214a Change BX_PANIC to BX_INFO when behaviour exactly matches Intel docs 2003-10-06 10:01:12 +00:00
Stanislav Shwartsman
9690ed763b // is not allowed in pure-C 2003-10-05 12:14:02 +00:00
Stanislav Shwartsman
149f8aef82 dos2unix fix 2003-10-05 10:05:05 +00:00
Stanislav Shwartsman
8bf447d0cd Implement a few 3DNOW instructions 2003-10-05 09:51:26 +00:00
Stanislav Shwartsman
3084a41abf Changes BX_PANIC to BX_INFO if Bochs behavour is exactly matches Intel docs 2003-10-04 20:48:13 +00:00
Stanislav Shwartsman
1e996cc329 According to Intel documentation instructions ARPL,LAR,LSL,SLDT/LLDT, 
STR/LTR,VERR/VERW are not recognized in v8086 or real mode and should
generate #UD exception
 2003-10-04 20:22:24 +00:00
Stanislav Shwartsman
03b41ad14f Small i387 structure size optimization 2003-10-04 11:04:10 +00:00
Stanislav Shwartsman
b50fb9e76e code simplification before FPU development 
print if Bochs supports 3DNOW to log file
 2003-09-27 20:58:46 +00:00
Stanislav Shwartsman
56beb4110c Little code optimization 2003-09-26 19:20:17 +00:00
Stanislav Shwartsman
15e84d0f5d dos2unix fixes 2003-09-26 16:07:38 +00:00
Stanislav Shwartsman
789db2603e Added P4 support to CPUID instruction 
Extracted CPUIS instructions to separate file
 2003-09-26 15:32:41 +00:00
Stanislav Shwartsman
bf2e0a109d Fixed compilation error (occures when fpu disabled) 2003-09-01 19:05:10 +00:00
Stanislav Shwartsman
7f570b0150 Added PNI new streaming extensions instructions 
PNI could be enabled by setting BX_SUPPORT_PNI in config.h
After the feature will be fully validation I'll also add configure option.

The implemntation is ~complete. I've missed only three FPU new opcodes of FUSTTP instruction and MONITOR/WAIT instructions.

Enjoy ! ;)
 2003-08-29 21:20:52 +00:00
Stanislav Shwartsman
254ad17328 Changes method of resolving opcode/attributes from group table 
New method more flexible and easy to understanding.
Reorganizing fetchdecode code and make it more easy and understandable
 2003-08-28 19:25:23 +00:00
Christophe Bothamy
cf70d952bc - reset also on other triple fault 2003-08-28 00:10:40 +00:00
Christophe Bothamy
9f31872f4b - implement reset on triple fault 
- old behavior (panic) can be used by setting BX_RESET_ON_TRIPLE_FAULT to 0 in config.h
 2003-08-24 23:39:33 +00:00
Christophe Bothamy
6977467ed7 - fix flaw in IO bitmap permission handling (anonymous patch) 
From the author (see bug #663320) :
  In the code there is a check to verify that an IO bitmap
  is defined (io_base > BX_CPU_THIS_PTR
  tr.cache.u.tss386.limit_scaled) but there is no check if
  an accessed IO port's address actually falls within the
  defined limit of the TSS segment. So if I define an IO
  bitmap with 100 entries, port 101 may or may not be
  allowed depending on whatever bytes follow the TSS in
  memory
 2003-08-24 23:14:52 +00:00
Christophe Bothamy
68f3624f66 - fix compile and segfault problems when configuring debugger and smp 2003-08-24 10:30:07 +00:00
Stanislav Shwartsman
79f46df971 separate APIC from CPU 2003-08-17 18:55:16 +00:00
Alexander Krisak
8559551001 iretd cpu instruction in real mode implemented, i hope this closes bugs 537047, 
603410, 637822, 664544, 687619.
 2003-08-17 18:15:04 +00:00
Stanislav Shwartsman
ecd8077b99 Fixed fetch qword function 2003-08-15 15:17:56 +00:00
Stanislav Shwartsman
60ca3ac674 ;; is not so necessary ;) 2003-08-15 13:18:53 +00:00