Stanislav Shwartsman
839b841c38
added register type to register source information in decoder
2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
...
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.
Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
f791802286
infrastructure change for several AVX handlers to support any VL and only 128/256
2013-09-21 20:40:57 +00:00
Stanislav Shwartsman
404b8b1475
move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark
2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
047b17d415
fixed typo in makefile
2013-09-21 10:52:18 +00:00
Stanislav Shwartsman
cd55ace8c8
fixed compilation err, rename opcode and handler functions for PUSHA/POPA instructions
2013-09-21 10:03:49 +00:00
Stanislav Shwartsman
2526282ed9
small additions for avx512
2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
3803ac7fbe
fixed evex override mscsr controls
2013-09-19 21:38:25 +00:00
Stanislav Shwartsman
0441f82b02
implement more AVX512 instructions
2013-09-19 20:35:55 +00:00
Stanislav Shwartsman
55f9155bc5
add new file
2013-09-19 18:32:39 +00:00
Stanislav Shwartsman
8b3a0acde9
implement first EVEX instructions - VADDPS/PD/SS/SD
2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
8e71a86542
seve vex prefix value to the indication of vex prefix used
2013-09-18 18:01:48 +00:00
Stanislav Shwartsman
da0e2baf22
avoid segfault when decoding incorrectly encoded kmask op
2013-09-17 21:01:24 +00:00
Stanislav Shwartsman
d169860f6c
added masked operations to simd_pfp.h, optimize simd_int.h, rewrite dpps instr using new masked op from simd_pfp.h
2013-09-17 20:49:26 +00:00
Stanislav Shwartsman
aa25c1db6a
name convention change - search and replace
2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
b6c39a3176
merge AVX and SSE .bochsrc options to single SIMD option which will configure SSE and AVX together
2013-09-16 19:50:36 +00:00
Stanislav Shwartsman
1cebe5f83d
rellback part of commit with xmm register access interface changes - doesn't work for big endian hosts
2013-09-16 19:10:42 +00:00
Volker Ruppert
ec4990a380
slirp / vnet: only one instance per Bochs session supported yet
2013-09-16 17:06:03 +00:00
Stanislav Shwartsman
0cb0acc30f
added evex decode tables - next step to populate them :)
2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
1e1fa45cac
fixed makefile after file rename
2013-09-08 20:16:38 +00:00
Stanislav Shwartsman
e4a99b4294
rename avx512_mask.cc
2013-09-08 20:15:52 +00:00
Stanislav Shwartsman
132714bf29
fixed compilation w/o EVEX support enabled
2013-09-08 19:45:46 +00:00
Stanislav Shwartsman
8881800b1f
enable avx-512 in init.cc
2013-09-08 19:35:37 +00:00
Stanislav Shwartsman
edc3e3edf9
Adding Id and Rev property to the new file
2013-09-08 19:22:07 +00:00
Stanislav Shwartsman
7297323c69
First step of AVX512 support implementation (simplest)
...
decode and implement KMASK manipulation instructions
disasm: coming soon
2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
6ddfe5fc3b
reorg avx opcodes in ia_opcodes.h. place v128 and v256 opcodes together. todo: find way to merge them sometimes
2013-09-07 18:52:31 +00:00
Stanislav Shwartsman
a6b85d9443
compress xop tables for vex.l - smaller binary size
2013-09-06 18:56:46 +00:00
Volker Ruppert
dbccb39fb7
fixed unused variable warning with BX_CPU_LEVEL <= 4
2013-09-06 06:44:05 +00:00
Stanislav Shwartsman
0fd4e3450c
update (c) for few files
2013-09-05 18:40:14 +00:00
Stanislav Shwartsman
2c9cf33b2f
update (c) for few files
2013-09-05 18:37:10 +00:00
Stanislav Shwartsman
69f947cef2
fixes and small optimizations for avx and xop decoding
2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
f36364bc65
it doesn't matter if it was vex or xop ...
2013-09-05 17:52:47 +00:00
Volker Ruppert
d943feaf8e
panic if cirrus support is requested but not available to avoid segfault
2013-09-05 07:38:22 +00:00
Volker Ruppert
7c0a261751
final fix for BX_CPU_LEVEL 4
2013-09-05 06:42:17 +00:00
Stanislav Shwartsman
897bf85494
fixed bug in fma4 decoding - found now thanks to new tables re-org
2013-09-04 18:37:49 +00:00
Stanislav Shwartsman
2f957bf142
re-arrange AVX/XOP table to avoid redundant multiplication in decode. TODO: compress the tables 2x using aliases
2013-09-04 18:36:01 +00:00
Stanislav Shwartsman
bb695fd5f5
remove redundant (and incorrect) check
2013-09-04 16:47:52 +00:00
Stanislav Shwartsman
5de4907f93
anotehr fix for Bochs compiled for cpu-level=4
2013-09-04 14:23:58 +00:00
Stanislav Shwartsman
81affbe328
fixed incorrect lock prefix detection
2013-08-30 20:08:04 +00:00
Stanislav Shwartsman
c2558f52d6
generic_cpuid: fixed xsave cpuid leaf when xsave is disabled (need to clear output)
2013-08-29 19:58:31 +00:00
Stanislav Shwartsman
59c65151f5
various fixes
2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
7e2ab5ca81
decode simplification for AMD XOP prefix
2013-08-28 19:56:19 +00:00
Stanislav Shwartsman
5d61c19b0b
evex support - step2
2013-08-27 20:47:24 +00:00
Stanislav Shwartsman
5fe5bf1ed6
fixed alias typo corrupting avx opcodes
2013-08-27 19:45:31 +00:00
Stanislav Shwartsman
c5f72033ad
correct vzeroupper opcode
2013-08-27 06:57:48 +00:00
Stanislav Shwartsman
735154a755
oops, typo bug in prev commit
2013-08-24 19:46:04 +00:00
Stanislav Shwartsman
65e6760915
small decode optimization
2013-08-24 19:29:43 +00:00
Stanislav Shwartsman
ba317a4ce1
fixed compilation when --enable-evex is ON
2013-08-24 18:28:09 +00:00
Stanislav Shwartsman
748a0da712
one more step in the way towards avx-512 which have more vector registers
2013-08-24 12:12:10 +00:00
Stanislav Shwartsman
25f99f76c3
remove test registers from disasm as well
2013-08-23 05:54:51 +00:00