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419 Commits

Author SHA1 Message Date
Stanislav Shwartsman
7a34f00f99 extracted fetchdecode into separated folder under cpu and also out of BX_CPU_C class into stand-alone module. Next step: wrap it up nicely and define clear interace to CPU model to minimize dependencies. Ideally I need fetchdecode to not include CPU at all 2016-06-12 21:23:48 +00:00
Stanislav Shwartsman
adc143684b implemented Intel architecture extensions published in recently published SDM 058: 
! Implemented UMIP: User Mode Instruction Prevention (don't allow execution of SLDT/SIDT/SGDT/STR/SMSW with CPL>0)
! Implemented RDPID instruction

Bugfixes in RDPKRU/WRPKRU instructions implementation (Protection Keys feature)
 2016-04-15 11:35:32 +00:00
Stanislav Shwartsman
e4832af5ab clean pkeys when not enabled to avoid side-effects 2016-03-19 21:15:56 +00:00
Stanislav Shwartsman
5b481fe34d correctly set up pkeys when enabling through cr4 2016-03-19 19:48:38 +00:00
Stanislav Shwartsman
bcb36e81fa experimental implementation of protection keys paging extension published in SDM rev054. to enable configure with --enable-protection-keys 2016-03-02 20:44:42 +00:00
Stanislav Shwartsman
8d13b61319 implemented TSC Scaling VMX feature according to timestamp-counter for virtualization whitepaper published by Intel 2015-09-30 18:44:01 +00:00
Stanislav Shwartsman
c44cb6ed81 more cases applicable for BX_TLB_ENTRY_OF 2015-09-22 20:10:22 +00:00
Stanislav Shwartsman
da39e57196 comment fixes 2015-09-08 19:14:58 +00:00
Stanislav Shwartsman
f6af0443bb small optimization and elimination of several defines from cpu.h - replace by inline functions and const variables 2015-07-13 20:24:14 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
e16c6eb30c preparations and interface definition for memory type support 2015-02-19 20:23:08 +00:00
Stanislav Shwartsman
5e6955c5e7 Major rewrite of memory access methods to avoid massive code duplication and enable inlining of memory access methods 2015-01-25 20:55:10 +00:00
Stanislav Shwartsman
63c3ed3f70 update (c) and fix instrumentation stub 2015-01-11 20:50:26 +00:00
Stanislav Shwartsman
3b237df41d Added far branch origin to bx_instr_far_branch instrumentation callback by user request 
Updated instrumentation examples
Fixed code duplication
 2015-01-11 20:45:39 +00:00
Stanislav Shwartsman
d82e51f947 added comment to RDPMC instr 2014-10-15 15:28:13 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
09254eb474 avx512 implementation fixes and next steps 2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
fd383435f0 - Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon). 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
 2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
69f947cef2 fixes and small optimizations for avx and xop decoding 2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
59c65151f5 various fixes 2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
2dbe81db51 first infrastructure changes to support EVEX prefix and AVX-512 extensions recently published by Intel 2013-07-26 12:50:56 +00:00
Stanislav Shwartsman
a277d60d89 implemented vmentering to non-active cpu state 2013-04-09 15:43:15 +00:00
Stanislav Shwartsman
d38fce8218 preparation for future extension in translate_linear - I would like to return data to caller through tlbEntry 2013-01-27 19:27:30 +00:00
Stanislav Shwartsman
4bed791ccb Added year 2013 to Copyright in all files already modified in new year 2013-01-19 20:45:03 +00:00
Stanislav Shwartsman
d93607cfe6 implemented pause threshold count in SVN + bugfix in SMAP 2013-01-08 21:03:22 +00:00
Stanislav Shwartsman
e7a2c9892c re-implement VTPF write using event handling interface as trap event (in preparation to more apic virtualization features) 2012-10-07 09:16:13 +00:00
Stanislav Shwartsman
f69bc016d2 vmx: nmi blocking after NMI event injection. better dbg print for VMEXIT 2012-10-04 16:15:58 +00:00
Stanislav Shwartsman
2ca0c6c677 Move INTR, Local APIC INTR and SVN VINTR into new event interface (hardest part) 
Minor speedup (of 1-2%) was observed due to new implementation
Remove obsolete dbg_take_irq function and dbg_force_interrupt function from CPU code, the functions were not working properly anyway
 2012-10-03 20:24:29 +00:00
Stanislav Shwartsman
49bb3ba8f5 some cleanups and optimizations with new event interface 2012-10-03 15:49:45 +00:00
Stanislav Shwartsman
40ba9c8d7b introducing new interface for handling CPU events based on vector of events and not on many not related variables. this is very initial implementation which takes into new interface only few events, more will code soon 2012-09-25 09:35:38 +00:00
Stanislav Shwartsman
74f5bb1934 WBINVD not necessary havw to flush ICACHE 2012-09-21 08:55:10 +00:00
Stanislav Shwartsman
2f3c7ff8e4 implemented SMAP (Supervisor Mode Access Protection) from [Intel Architecture Instruction Set Extensions Programming Reference] rev14 
fixed enabling of ADX extensions in generic CPUID when enabled through .bochsrc

Small code cleanups on the way to implementation of APIC Registers Virtualization features disclosed in recent Intel SDM rev043
 2012-09-10 15:22:26 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
4d03b57291 Allow larger quantum value for SMP simulations (up to 32) 
Update CHANGES
 2012-08-02 20:48:27 +00:00
Stanislav Shwartsman
e0729e32b8 fixed bug 3548108 VMEXIT instruction length Not always getting updated 2012-07-26 16:03:26 +00:00
Stanislav Shwartsman
f9540f1c24 - Improved CPU status restore after restoring from Bochs saved image 
- Changed many BX_ERROR messages about VMX VMEXIT takesn to BX_DEBUG
 2012-05-19 20:36:40 +00:00
Stanislav Shwartsman
279c61dc67 updated + fixed instrumentation example for instr histogram, code cleanup in the cpu 2012-03-28 21:11:19 +00:00
Stanislav Shwartsman
90fc12d9e4 switching between compatibility and long64 mode also affect SS.BASE which is always zero in long64 mode 2012-03-27 15:21:40 +00:00
Stanislav Shwartsman
e7a4a1bec8 surprisingly, opensuse 12.1 requre alignment check support in hardware so I can't disable it by default for all configurations. 
but in case you want a few %% of extra emulation performance - it is still possible to disable it with configure option.
most guests I saw do not use it !
 2012-03-26 19:33:38 +00:00
Stanislav Shwartsman
547678e8bd fixed compilation error in 386 config. also fixed bugs in tasking code found by new assertion added in stack.cc new code 2012-03-26 19:05:58 +00:00
Stanislav Shwartsman
d4688e8b95 - Do not compile support for alignment check (#AC exception) by default 
for CPU emulation performance reasons, the alignment check compilation
    still can be enabled using configure option --enable-alignment-check.

There is no software in the world which enable #AC exception checking, this
x86 feature is completely legacy but its emulation support costs up to 3-5%
emulation speed.

The checking for #AC exception enable still will be done, if

 CPL == 3, EFLAGS.AC = 1 and CR0.AM = 1

but the alignment check is not compiled in, the Bochs will PANIC with corresponding message.
You can press 'always continue' and ignore the PANIC, the simulation will continue as if alignment checking is not enabled.
 2012-03-25 19:07:17 +00:00
Stanislav Shwartsman
3ca29cbdf3 stack direct access optimization - 5% emu speedup to all 32-bit guests, for 64-bit guests speedup is less because they have less stack accesses 2012-03-25 11:54:32 +00:00
Stanislav Shwartsman
5a33b1be84 mvoed MWAIT_IS_NOP option from CPUID to CPU - it has meaning even if CPUID tree is not used because CPU is configured with CPUDB pre-defined configuration 2012-03-15 19:46:57 +00:00
Stanislav Shwartsman
9461797886 added extra param to debugger phy access callback + cleanup in vmexit functions 2012-01-17 21:50:15 +00:00
Stanislav Shwartsman
f5d55f5eb6 - Implemented Task Switch intercept in SVM, cleanup in task switch handling code 
- Changed (c) year in several cpu files
- Cleanup and indent fixes in VMX code
 2012-01-11 20:21:29 +00:00
Stanislav Shwartsman
76ee7b499b svm updates 2012-01-08 14:09:51 +00:00
Stanislav Shwartsman
269d5e3443 more SVM fixes 2012-01-01 20:26:23 +00:00
Stanislav Shwartsman
93523a657d remove patch that always kept IF set after HLT - not needed anymore 2011-12-30 08:50:01 +00:00