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232 Commits

Author SHA1 Message Date
Stanislav Shwartsman
690bae9a12 add fields and bits for newly announced x86 features and vmx state 2024-04-26 22:13:08 +03:00
Stanislav Shwartsman
a565f9a754 implement Flexible UIRET (AKA UIRET_UIF) announced in 319433-052 2024-04-26 21:53:03 +03:00
Stanislav Shwartsman
69fa93e75b implement MONITORLESS MWAIT support (announced in 319433-052) 
rework CPUDB classes to avoid code duplication for MONITOR/MWAIT leaf
 2024-04-26 21:29:53 +03:00
Torinde
8757c36e1c
Update cpuid.cc - label and abbreviation corrections SMX, MPX (#301) 
Memory Protection Extensions - add MPX abbreviation

SMX: Secure Virtual Machine Technology - bit6 is for SMX, but [it's
meaning](https://en.wikipedia.org/wiki/CPUID) is Safer Mode Extensions
(part of TXT). Not Secure Virtual Machine Technology (which is already
listed elsewhere as SVM).
 2024-04-15 09:00:58 +03:00
Vort
c2891e5ff6
Fix Windows 11 boot, #280 (partial revert of b24bf1d) (#285) 2024-03-15 18:02:07 +02:00
Stanislav Shwartsman
d350c008e2
add softfloat3e library to Bochs to replace old softfloat2 (to get fp… (#259) 
…16 support)

with a lot of my updates, cleanups and extensions for x86 features like
denormal and/or undeflow/overflow handling

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2024-03-10 17:10:55 +02:00
Shwartsman
6f4f217a08 implemented AMX_FP16 and aMX_COMPLEX, fixes for daz handling in AVX_NE_CONVERT FB16 
updated CHANGES
 2024-01-12 12:38:31 +02:00
Stanislav Shwartsman
3a02e85599
AMX support (#212) 2024-01-10 20:13:25 +02:00
Shwartsman
b24bf1dae2 CPUID: Added Xeon Sapphire Rapids CPU definition 
Features PKS, WAITPKG, UINTR, AVX512_BF16, MOVDIRI/MOVDIR64, LA57, SERIALIZE and more
Not yet supported but will be added in future: AVX512_FP16, AMX
 2024-01-05 19:54:37 +02:00
Stanislav Shwartsman
e3612c30f8 Implement support for LA57 and 5-level paging 2023-12-29 14:48:38 +02:00
Shwartsman
fc919cd132 use true/false instead of 0/1 for bool in the cpu code 2023-12-19 20:44:56 +02:00
Stanislav Shwartsman
54e88eee92 more correction for CPUID leaf 0xD 2023-12-18 15:58:18 +02:00
Shwartsman
d794b516e1 rewrite XSAVE/XRESTORE CPUID leaf reporting, 
fixed several bugs and made code correct for all future XSAVE extensions
 2023-12-18 11:35:55 +02:00
Stanislav Shwartsman
54831068df
implement RDMSRLIST/WRMSRLIST instructions (+related VMX extensions) (#176) 2023-12-16 21:59:34 +02:00
Shwartsman
e68ae599af added comments and consts for CPUID definitions 2023-12-16 10:10:48 +02:00
Shwartsman
a1060a0825 cleanups in CPUDB cpuid definitions 2023-12-03 16:46:39 +02:00
Stanislav Shwartsman
00e8e0bca0 implemented MOVDIR64B instruction and enabled in TigerLake model 2023-12-01 18:03:25 +02:00
Stanislav Shwartsman
2e89b9bcba
implemented WAITPKG instruction set (#150) 
still missing : UMWAIT/TPAUSE should set CF flag if it was using OS
deadline and woken up after deadline (i.e. not from monitored store)
also not clear in the spec: should UWAITX/TPAUSE always wait until
deadline due to 'while(tsc<deadline)' statement ?
+include small fixes for AMD's MONITORX/MWAITX
 2023-12-01 18:00:03 +02:00
Stanislav Shwartsman
280303d76c
initial code for UINTR implementation (#138) 
First step into implementing UINTR - User Level Interrupts ISA extension
To be continued

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-25 16:43:47 +02:00
Stanislav Shwartsman
f90fdbc353 add methods to query local apic state 2023-11-21 15:43:38 +02:00
Shwartsman
04ffb4cf03 fixed compilation with .conf.nothing 2023-11-19 23:55:52 +02:00
Stanislav Shwartsman
f5b54a4d33
Implemented MOVDIRI instruction (#129) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-11-11 20:30:12 +02:00
Stanislav Shwartsman
18deee022f
make CPU to use C++ template for implementation of CPU methods (#115) 
this allow to remove a lot of code from CPU common methods
 2023-10-30 06:57:16 +02:00
Shwartsman
221cac7972 fixed compilation with no EVEX 2023-10-16 08:14:03 +03:00
Stanislav Shwartsman
a3d2fec111 Merge branch 'master' of https://github.com/bochs-emu/Bochs 2023-10-16 00:19:45 +03:00
Stanislav Shwartsman
035695f73c define CPU feature's enum together with feature name in one place 2023-10-15 23:56:11 +03:00
Stanislav Shwartsman
8e6bdcb4d9 define CPU feature's enum together with feature name in one place 2023-10-15 23:43:14 +03:00
Stanislav Shwartsman
8316d7698f
implemented Linear Address Separation extension (LASS) (#90) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-15 14:32:01 +03:00
Stanislav Shwartsman
ffa64461ab
implementation of AVX-NE-CONVERT ISA (#89) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-14 14:55:12 +03:00
Stanislav Shwartsman
9917227a56 enable CPUID reporting for recently added ISA extensions 
more steps towards more generic CPUID code
 2023-10-12 21:48:09 +03:00
Stanislav Shwartsman
dd7d4dbd82 implement SERIALIZE instruction 
enable CPUID reporting for all recently added ISA extensions
 2023-10-12 14:46:27 +03:00
Stanislav Shwartsman
4a309478f9
SHA512 instructions implemented (#88) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 21:33:16 +03:00
Stanislav Shwartsman
3234e9b88e
implemented AVX VNNI INT16 ISA extension (#87) 
Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-10 20:22:07 +03:00
Stanislav Shwartsman
44eea71f37
implemented SM3 instructions (#84) 
add rol/ror methods to scalar_arith.h and use in more places

---------

Co-authored-by: Stanislav Shwartsman <sshwarts@users.sourceforge.net>
 2023-10-07 21:34:04 +03:00
Stanislav Shwartsman
7e909a6fa5 rename CPUID flags to match leaf numbers 2023-10-07 18:10:20 +03:00
Shwartsman
6307786ded automatically determine MCE/MCA CPUID flags 2023-10-07 01:51:18 +03:00
Shwartsman
6d83b5239e another code duplication fix in CPUDB code 2023-10-07 01:36:05 +03:00
Shwartsman
20dfe7c7d0 improve comment 2023-10-07 01:09:22 +03:00
Shwartsman
672c93c7c4 reduce code duplication using new CPUID methods 2023-10-07 01:02:39 +03:00
Shwartsman
5fc6302b1b add one more CPUID method for future use + fix compilation after prev commit 2023-10-07 00:10:18 +03:00
Shwartsman
f50419429d Fix code duplication for CPUID ECX leaf 0x1, implement with common function for all CPUs 2023-10-06 22:53:30 +03:00
Stanislav Shwartsman
0e4524f38f Implemented CMPccXADD instructions 2022-10-08 20:04:22 +03:00
Stanislav Shwartsman
a56144833a add support for AVX encoded VNNI INT8 extensions 2022-10-02 23:00:46 +03:00
Stanislav Shwartsman
3a20495db8 implemented WRMSRNS extension - Non Serializing version of WRMSR opcode 2022-10-02 22:16:02 +03:00
Stanislav Shwartsman
9f76eaacea implemented AVX IFMA instructions 2022-10-02 22:08:20 +03:00
Stanislav Shwartsman
1e4f1624c8 remove trailing whitespace from source files 2022-08-23 21:46:04 +03:00
Stanislav Shwartsman
2ab50c7d66 solve code duplication between different cpudb models 2021-02-16 18:57:49 +00:00
Stanislav Shwartsman
7cc9cffeed remove siminterface.h from bochs.h and include it only where required 2021-01-30 19:40:18 +00:00
Stanislav Shwartsman
1bf18b8aae ! CPUID: Added TigerLake CPU definition (features CET and CLWB support) 
- CPU code refactor, remove uses of bx_bool datatype and use C++ classic bool instead.
  This enable better compiler optimizations and reduce binary size
 2021-01-30 08:35:35 +00:00
Stanislav Shwartsman
e15012cfcf fix code duplication in <limiting max cpuid leaf to 0x02 for winnt> feature 2021-01-02 16:28:51 +00:00