fixed compilation with .conf.nothing
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a7a443ab46
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04ffb4cf03
@ -441,8 +441,10 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_1_ecx(Bit32u extra) const
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// [11:11] reserved
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// [12:12] FMA Instructions support
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#if BX_SUPPORT_AVX
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if (is_cpu_extension_supported(BX_ISA_AVX_FMA))
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ecx |= BX_CPUID_STD1_ECX_FMA;
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#endif
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// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
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if (is_cpu_extension_supported(BX_ISA_CMPXCHG16B))
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@ -501,8 +503,10 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_1_ecx(Bit32u extra) const
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ecx |= BX_CPUID_STD1_ECX_AVX;
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// [29:29] AVX F16C - Float16 conversion support
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#if BX_SUPPORT_AVX
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if (is_cpu_extension_supported(BX_ISA_AVX_F16C))
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ecx |= BX_CPUID_STD1_ECX_AVX_F16C;
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#endif
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// [30:30] RDRAND instruction
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if (is_cpu_extension_supported(BX_ISA_RDRAND))
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@ -1128,8 +1132,10 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_subleaf_1_eax(Bit32u extra) const
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// [3:3] RAO-INT
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// [4:4] AVX VNNI
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#if BX_SUPPORT_AVX
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if (is_cpu_extension_supported(BX_ISA_AVX_VNNI))
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eax |= BX_CPUID_STD7_SUBLEAF1_EAX_AVX_VNNI;
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#endif
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// [5:5] AVX512_BF16 conversion instructions support
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#if BX_SUPPORT_EVEX
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@ -1163,8 +1169,10 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_subleaf_1_eax(Bit32u extra) const
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// [22:22] HRESET and CPUID leaf 0x20 support
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// [23:23] AVX IFMA support
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#if BX_SUPPORT_AVX
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if (is_cpu_extension_supported(BX_ISA_AVX_IFMA))
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eax |= BX_CPUID_STD7_SUBLEAF1_EAX_AVX_IFMA;
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#endif
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// [25:24] reserved
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// [26:26] LAM: Linear Address Masking
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@ -1184,20 +1192,24 @@ Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_subleaf_1_edx(Bit32u extra) const
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// [3:0] reserved
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// [4:4] AVX_VNNI_INT8 support
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#if BX_SUPPORT_AVX
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if (is_cpu_extension_supported(BX_ISA_AVX_VNNI_INT8))
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edx |= BX_CPUID_STD7_SUBLEAF1_EDX_AVX_VNNI_INT8;
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// [5:5] AVX_NE_CONVERT instructions
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if (is_cpu_extension_supported(BX_ISA_AVX_NE_CONVERT))
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edx |= BX_CPUID_STD7_SUBLEAF1_EDX_AVX_NE_CONVERT;
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#endif
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// [7:6] reserved
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// [8:8] AMX-COMPLEX instructions
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// [9:9] reserved
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// [10:10] AVX-VNNI-INT16 instructions
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#if BX_SUPPORT_AVX
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if (is_cpu_extension_supported(BX_ISA_AVX_VNNI_INT16))
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edx |= BX_CPUID_STD7_SUBLEAF1_EDX_AVX_VNNI_INT16;
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#endif
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// [13:11] reserved
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// [14:14] PREFETCHITI: PREFETCHIT0/T1 instruction
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