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define CPU feature's enum together with feature name in one place

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This commit is contained in:
Stanislav Shwartsman 2023-10-15 23:43:14 +03:00
parent e7910a30a0
commit 8e6bdcb4d9
9 changed files with 149 additions and 237 deletions
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1
bochs/cpu/cpudb/intel/core2_penryn_t9600.cc
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@ -53,7 +53,6 @@ core2_penryn_t9600_t::core2_penryn_t9600_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
#if BX_SUPPORT_VMX
enable_cpu_extension(BX_ISA_VMX);
#endif
enable_cpu_extension(BX_ISA_SMX);
enable_cpu_extension(BX_ISA_CLFLUSH);
enable_cpu_extension(BX_ISA_DEBUG_EXTENSIONS);
enable_cpu_extension(BX_ISA_VME);

1
bochs/cpu/cpudb/intel/corei3_cnl.cc
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@ -108,7 +108,6 @@ corei3_cnl_t::corei3_cnl_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
enable_cpu_extension(BX_ISA_AVX512_DQ);
enable_cpu_extension(BX_ISA_AVX512_CD);
enable_cpu_extension(BX_ISA_AVX512_BW);
enable_cpu_extension(BX_ISA_AVX512_VL);
enable_cpu_extension(BX_ISA_AVX512_IFMA52);
enable_cpu_extension(BX_ISA_AVX512_VBMI);
#endif

1
bochs/cpu/cpudb/intel/corei7_icelake-u.cc
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@ -109,7 +109,6 @@ corei7_icelake_t::corei7_icelake_t(BX_CPU_C *cpu):
enable_cpu_extension(BX_ISA_GFNI);
enable_cpu_extension(BX_ISA_VAES_VPCLMULQDQ);
enable_cpu_extension(BX_ISA_AVX512);
enable_cpu_extension(BX_ISA_AVX512_VL);
enable_cpu_extension(BX_ISA_AVX512_DQ);
enable_cpu_extension(BX_ISA_AVX512_CD);
enable_cpu_extension(BX_ISA_AVX512_BW);

1
bochs/cpu/cpudb/intel/corei7_skylake-x.cc
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@ -107,7 +107,6 @@ corei7_skylake_x_t::corei7_skylake_x_t(BX_CPU_C *cpu): bx_cpuid_t(cpu)
enable_cpu_extension(BX_ISA_AVX512_DQ);
enable_cpu_extension(BX_ISA_AVX512_CD);
enable_cpu_extension(BX_ISA_AVX512_BW);
enable_cpu_extension(BX_ISA_AVX512_VL);
#endif
enable_cpu_extension(BX_ISA_CLFLUSHOPT);
enable_cpu_extension(BX_ISA_CLWB);

1
bochs/cpu/cpudb/intel/tigerlake.cc
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@ -109,7 +109,6 @@ tigerlake_t::tigerlake_t(BX_CPU_C *cpu):
enable_cpu_extension(BX_ISA_GFNI);
enable_cpu_extension(BX_ISA_VAES_VPCLMULQDQ);
enable_cpu_extension(BX_ISA_AVX512);
enable_cpu_extension(BX_ISA_AVX512_VL);
enable_cpu_extension(BX_ISA_AVX512_DQ);
enable_cpu_extension(BX_ISA_AVX512_CD);
enable_cpu_extension(BX_ISA_AVX512_BW);

120
bochs/cpu/cpuid.cc
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@ -27,123 +27,11 @@
#include "param_names.h"
#include "cpuid.h"
static const char *cpu_feature_name[] =
{
"386ni", // BX_ISA_386
"x87", // BX_ISA_X87
"486ni", // BX_ISA_486
"pentium_ni", // BX_ISA_PENTIUM
"p6ni", // BX_ISA_P6
"mmx", // BX_ISA_MMX
"3dnow!", // BX_ISA_3DNOW
"debugext", // BX_ISA_DEBUG_EXTENSIONS
"vme", // BX_ISA_VME
"pse", // BX_ISA_PSE
"pae", // BX_ISA_PAE
"pge", // BX_ISA_PGE
"pse36", // BX_ISA_PSE36
"mtrr", // BX_ISA_MTRR
"pat", // BX_ISA_PAT
"legacy_syscall_sysret", // BX_ISA_SYSCALL_SYSRET_LEGACY
"sysenter_sysexit", // BX_ISA_SYSENTER_SYSEXIT
"clflush", // BX_ISA_CLFLUSH
"clflushopt", // BX_ISA_CLFLUSHOPT
"clwb", // BX_ISA_CLWB
"cldemote", // BX_ISA_CLDEMOTE
"sse", // BX_ISA_SSE
"sse2", // BX_ISA_SSE2
"sse3", // BX_ISA_SSE3
"ssse3", // BX_ISA_SSSE3
"sse4_1", // BX_ISA_SSE4_1
"sse4_2", // BX_ISA_SSE4_2
"popcnt", // BX_ISA_POPCNT
"mwait", // BX_ISA_MONITOR_MWAIT
"mwaitx", // BX_ISA_MONITORX_MWAITX
"waitpkg", // BX_ISA_WAITPKG
"vmx", // BX_ISA_VMX
"smx", // BX_ISA_SMX
"longmode", // BX_ISA_LONG_MODE
"lm_lahf_sahf", // BX_ISA_LM_LAHF_SAHF
"nx", // BX_ISA_NX
"1g_pages", // BX_ISA_1G_PAGES
"cmpxhg16b", // BX_ISA_CMPXCHG16B
"rdtscp", // BX_ISA_RDTSCP
"ffxsr", // BX_ISA_FFXSR
"xsave", // BX_ISA_XSAVE
"xsaveopt", // BX_ISA_XSAVEOPT
"xsavec", // BX_ISA_XSAVEC
"xsaves", // BX_ISA_XSAVES
"aes_pclmulqdq", // BX_ISA_AES_PCLMULQDQ
"vaes_vpclmulqdq", // BX_ISA_VAES_VPCLMULQDQ
"movbe", // BX_ISA_MOVBE
"fsgsbase", // BX_ISA_FSGSBASE
"invpcid", // BX_ISA_INVPCID
"avx", // BX_ISA_AVX
"avx2", // BX_ISA_AVX2
"avx_f16c", // BX_ISA_AVX_F16C
"avx_fma", // BX_ISA_AVX_FMA
"altmovcr8", // BX_ISA_ALT_MOV_CR8
"sse4a", // BX_ISA_SSE4A
"misaligned_sse", // BX_ISA_MISALIGNED_SSE
"lzcnt", // BX_ISA_LZCNT
"bmi1", // BX_ISA_BMI1
"bmi2", // BX_ISA_BMI2
"fma4", // BX_ISA_FMA4
"xop", // BX_ISA_XOP
"tbm", // BX_ISA_TBM
"svm", // BX_ISA_SVM
"rdrand", // BX_ISA_RDRAND
"adx", // BX_ISA_ADX
"smap", // BX_ISA_SMAP
"rdseed", // BX_ISA_RDSEED
"sha", // BX_ISA_SHA
"sha512", // BX_ISA_SHA512
"gfni", // BX_ISA_GFNI
"sm3", // BX_ISA_SM3
"sm4", // BX_ISA_SM4
"avx512", // BX_ISA_AVX512
"avx512cd", // BX_ISA_AVX512_CD
"avx512pf", // BX_ISA_AVX512_PF
"avx512er", // BX_ISA_AVX512_ER
"avx512dq", // BX_ISA_AVX512_DQ
"avx512bw", // BX_ISA_AVX512_BW
"avx512vl", // BX_ISA_AVX512_VL
"avx512vbmi", // BX_ISA_AVX512_VBMI
"avx512vbmi2", // BX_ISA_AVX512_VBMI2
"avx512ifma52", // BX_ISA_AVX512_IFMA52
"avx512vpopcnt", // BX_ISA_AVX512_VPOPCNTDQ
"avx512vnni", // BX_ISA_AVX512_VNNI
"avx512bitalg", // BX_ISA_AVX512_BITALG
"avx512vp2intersect", // BX_ISA_AVX512_VP2INTERSECT
"avx512bf16", // BX_ISA_AVX512_BF16
"avx_ifma", // BX_ISA_AVX_IFMA
"avx_vnni", // BX_ISA_AVX_VNNI
"avx_vnni_int8", // BX_ISA_AVX_VNNI_INT8
"avx_vnni_int16", // BX_ISA_AVX_VNNI_INT16
"avx_ne_convert", // BX_ISA_AVX_NE_CONVERT
"xapic", // BX_ISA_XAPIC
"x2apic", // BX_ISA_X2APIC
"xapicext", // BX_ISA_XAPICEXT
"pcid", // BX_ISA_PCID
"smep", // BX_ISA_SMEP
"tsc_adjust", // BX_ISA_TSC_ADJUST
"tsc_deadline", // BX_ISA_TSC_DEADLINE
"fopcode_deprecation", // BX_ISA_FOPCODE_DEPRECATION
"fcs_fds_deprecation", // BX_ISA_FCS_FDS_DEPRECATION
"fdp_deprecation", // BX_ISA_FDP_DEPRECATION
"pku", // BX_ISA_PKU
"pks", // BX_ISA_PKS
"umip", // BX_ISA_UMIP
"lass", // BX_ISA_LASS
"rdpid", // BX_ISA_RDPID
"tce", // BX_ISA_TCE
"clzero", // BX_ISA_CLZERO
"sca_mitigations", // BX_ISA_SCA_MITIGATIONS
"cet", // BX_ISA_CET
"wrmsrns", // BX_ISA_WRMSRNS
"cmpccxadd", // BX_ISA_CMPCCXADD
"serialize", // BX_ISA_SERIALIZE
static const char *cpu_feature_name[BX_ISA_EXTENSION_LAST] = {
#define x86_feature(isa, feature_name) #feature_name,
#include "decoder/features.h"
};
#undef x86_feature
const char *get_cpu_feature_name(unsigned feature) { return cpu_feature_name[feature]; }

119
bochs/cpu/decoder/decoder.h
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@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2016-2020 The Bochs Project
// Copyright (C) 2016-2023 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -24,122 +24,11 @@
// x86 Arch features
enum x86_feature_name {
BX_ISA_386 = 0, /* 386 or earlier instruction */
BX_ISA_X87, /* FPU (X87) instruction */
BX_ISA_486, /* 486 new instruction */
BX_ISA_PENTIUM, /* Pentium new instruction */
BX_ISA_P6, /* P6 new instruction */
BX_ISA_MMX, /* MMX instruction */
BX_ISA_3DNOW, /* 3DNow! instruction (AMD) */
BX_ISA_DEBUG_EXTENSIONS, /* Debug Extensions support */
BX_ISA_VME, /* VME support */
BX_ISA_PSE, /* PSE support */
BX_ISA_PAE, /* PAE support */
BX_ISA_PGE, /* Global Pages support */
BX_ISA_PSE36, /* PSE-36 support */
BX_ISA_MTRR, /* MTRR support */
BX_ISA_PAT, /* PAT support */
BX_ISA_SYSCALL_SYSRET_LEGACY, /* SYSCALL/SYSRET in legacy mode (AMD) */
BX_ISA_SYSENTER_SYSEXIT, /* SYSENTER/SYSEXIT instruction */
BX_ISA_CLFLUSH, /* CLFLUSH instruction */
BX_ISA_CLFLUSHOPT, /* CLFLUSHOPT instruction */
BX_ISA_CLWB, /* CLWB instruction */
BX_ISA_CLDEMOTE, /* CLDEMOTE instruction */
BX_ISA_SSE, /* SSE instruction */
BX_ISA_SSE2, /* SSE2 instruction */
BX_ISA_SSE3, /* SSE3 instruction */
BX_ISA_SSSE3, /* SSSE3 instruction */
BX_ISA_SSE4_1, /* SSE4_1 instruction */
BX_ISA_SSE4_2, /* SSE4_2 instruction */
BX_ISA_POPCNT, /* POPCNT instruction */
BX_ISA_MONITOR_MWAIT, /* MONITOR/MWAIT instruction */
BX_ISA_MONITORX_MWAITX, /* MONITORX/MWAITX instruction (AMD) */
BX_ISA_WAITPKG, /* TPAUSE/UMONITOR/UMWAIT instructions */
BX_ISA_VMX, /* VMX instruction */
BX_ISA_SMX, /* SMX instruction */
BX_ISA_LONG_MODE, /* Long Mode (x86-64) support */
BX_ISA_LM_LAHF_SAHF, /* Long Mode LAHF/SAHF instruction */
BX_ISA_NX, /* No-Execute support */
BX_ISA_1G_PAGES, /* 1Gb pages support */
BX_ISA_CMPXCHG16B, /* CMPXCHG16B instruction */
BX_ISA_RDTSCP, /* RDTSCP instruction */
BX_ISA_FFXSR, /* EFER.FFXSR support */
BX_ISA_XSAVE, /* XSAVE/XRSTOR extensions instruction */
BX_ISA_XSAVEOPT, /* XSAVEOPT instruction */
BX_ISA_XSAVEC, /* XSAVEC instruction */
BX_ISA_XSAVES, /* XSAVES instruction */
BX_ISA_AES_PCLMULQDQ, /* AES+PCLMULQDQ instructions */
BX_ISA_VAES_VPCLMULQDQ, /* Wide vector versions of AES+PCLMULQDQ instructions */
BX_ISA_MOVBE, /* MOVBE instruction */
BX_ISA_FSGSBASE, /* FS/GS BASE access instruction */
BX_ISA_INVPCID, /* INVPCID instruction */
BX_ISA_AVX, /* AVX instruction */
BX_ISA_AVX2, /* AVX2 instruction */
BX_ISA_AVX_F16C, /* AVX F16 convert instruction */
BX_ISA_AVX_FMA, /* AVX FMA instruction */
BX_ISA_ALT_MOV_CR8, /* LOCK CR0 access CR8 (AMD) */
BX_ISA_SSE4A, /* SSE4A instruction (AMD) */
BX_ISA_MISALIGNED_SSE, /* Misaligned SSE (AMD) */
BX_ISA_LZCNT, /* LZCNT instruction */
BX_ISA_BMI1, /* BMI1 instruction */
BX_ISA_BMI2, /* BMI2 instruction */
BX_ISA_FMA4, /* FMA4 instruction (AMD) */
BX_ISA_XOP, /* XOP instruction (AMD) */
BX_ISA_TBM, /* TBM instruction (AMD) */
BX_ISA_SVM, /* SVM instruction (AMD) */
BX_ISA_RDRAND, /* RDRAND instruction */
BX_ISA_ADX, /* ADCX/ADOX instruction */
BX_ISA_SMAP, /* SMAP support */
BX_ISA_RDSEED, /* RDSEED instruction */
BX_ISA_SHA, /* SHA instruction */
BX_ISA_SHA512, /* SHA512 instruction */
BX_ISA_GFNI, /* GFNI instruction */
BX_ISA_SM3, /* SM3 instruction */
BX_ISA_SM4, /* SM4 instruction */
BX_ISA_AVX512, /* AVX-512 instruction */
BX_ISA_AVX512_CD, /* AVX-512 Conflict Detection instruction */
BX_ISA_AVX512_PF, /* AVX-512 Sparse Prefetch instruction */
BX_ISA_AVX512_ER, /* AVX-512 Exponential/Reciprocal instruction */
BX_ISA_AVX512_DQ, /* AVX-512DQ instruction */
BX_ISA_AVX512_BW, /* AVX-512 Byte/Word instruction */
BX_ISA_AVX512_VL, /* AVX-512 Vector Length extensions */
BX_ISA_AVX512_VBMI, /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
BX_ISA_AVX512_VBMI2, /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
BX_ISA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */
BX_ISA_AVX512_VPOPCNTDQ, /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
BX_ISA_AVX512_VNNI, /* AVX-512 VNNI Instructions */
BX_ISA_AVX512_BITALG, /* AVX-512 BITALG Instructions */
BX_ISA_AVX512_VP2INTERSECT, /* AVX-512 VP2INTERSECT Instructions */
BX_ISA_AVX512_BF16, /* AVX-512 BF16 Instructions */
BX_ISA_AVX_IFMA, /* AVX encoded IFMA Instructions */
BX_ISA_AVX_VNNI, /* AVX encoded VNNI Instructions */
BX_ISA_AVX_VNNI_INT8, /* AVX encoded VNNI-INT8 Instructions */
BX_ISA_AVX_VNNI_INT16, /* AVX encoded VNNI-INT16 Instructions */
BX_ISA_AVX_NE_CONVERT, /* AVX-NE-CONVERT Instructions */
BX_ISA_XAPIC, /* XAPIC support */
BX_ISA_X2APIC, /* X2APIC support */
BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */
BX_ISA_PCID, /* PCID pages support */
BX_ISA_SMEP, /* SMEP support */
BX_ISA_TSC_ADJUST, /* TSC-Adjust MSR */
BX_ISA_TSC_DEADLINE, /* TSC-Deadline */
BX_ISA_FOPCODE_DEPRECATION, /* FOPCODE Deprecation - FOPCODE update on unmasked x87 exception only */
BX_ISA_FCS_FDS_DEPRECATION, /* FCS/FDS Deprecation */
BX_ISA_FDP_DEPRECATION, /* FDP Deprecation - FDP update on unmasked x87 exception only */
BX_ISA_PKU, /* User-Mode Protection Keys */
BX_ISA_PKS, /* Supervisor-Mode Protection Keys */
BX_ISA_UMIP, /* User-Mode Instructions Prevention */
BX_ISA_LASS, /* Linear Address Separation */
BX_ISA_RDPID, /* RDPID Support */
BX_ISA_TCE, /* Translation Cache Extensions (TCE) support (AMD) */
BX_ISA_CLZERO, /* CLZERO instruction support (AMD) */
BX_ISA_SCA_MITIGATIONS, /* SCA Mitigations */
BX_ISA_CET, /* Control Flow Enforcement */
BX_ISA_WRMSRNS, /* Non-Serializing version of WRMSR */
BX_ISA_CMPCCXADD, /* CMPccXADD instructions */
BX_ISA_SERIALIZE, /* SERIALIZE instruction */
#define x86_feature(isa, feature_name) isa,
#include "features.h"
BX_ISA_EXTENSION_LAST
};
#undef x86_feature
#define BX_ISA_EXTENSIONS_ARRAY_SIZE (4)

141
bochs/cpu/decoder/features.h Normal file
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@ -0,0 +1,141 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2023 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
/////////////////////////////////////////////////////////////////////////
#ifndef BX_X86_FEATURES_H
#define BX_X86_FEATURES_H
x86_feature(BX_ISA_386, "386ni") /* 386 or earlier instruction */
x86_feature(BX_ISA_X87, "x87") /* FPU (x87) instruction */
x86_feature(BX_ISA_486, "486ni") /* 486 new instruction */
x86_feature(BX_ISA_PENTIUM, "pentium_ni") /* Pentium new instruction */
x86_feature(BX_ISA_P6, "p6ni") /* P6 new instruction */
x86_feature(BX_ISA_MMX, "mmx") /* MMX instruction */
x86_feature(BX_ISA_3DNOW, "3dnow") /* 3DNow! instruction (AMD) */
x86_feature(BX_ISA_DEBUG_EXTENSIONS, "debugext") /* Debug Extensions support */
x86_feature(BX_ISA_VME, "vme") /* VME support */
x86_feature(BX_ISA_PSE, "pse") /* PSE support */
x86_feature(BX_ISA_PAE, "pae") /* PAE support */
x86_feature(BX_ISA_PGE, "pge") /* Global Pages support */
x86_feature(BX_ISA_PSE36, "pse36") /* PSE-36 support */
x86_feature(BX_ISA_MTRR, "mtrr") /* MTRR support */
x86_feature(BX_ISA_PAT, "pat") /* PAT support */
x86_feature(BX_ISA_SYSCALL_SYSRET_LEGACY, "legacy_syscall_sysret") /* SYSCALL/SYSRET in legacy mode (AMD) */
x86_feature(BX_ISA_SYSENTER_SYSEXIT, "sysenter_sysexit") /* SYSENTER/SYSEXIT instruction */
x86_feature(BX_ISA_CLFLUSH, "clflush") /* CLFLUSH instruction */
x86_feature(BX_ISA_CLFLUSHOPT, "clflushopt") /* CLFLUSHOPT instruction */
x86_feature(BX_ISA_CLWB, "clwb") /* CLWB instruction */
x86_feature(BX_ISA_CLDEMOTE, "cldemote") /* CLDEMOTE instruction */
x86_feature(BX_ISA_SSE, "sse") /* SSE instruction */
x86_feature(BX_ISA_SSE2, "sse2") /* SSE2 instruction */
x86_feature(BX_ISA_SSE3, "sse3") /* SSE3 instruction */
x86_feature(BX_ISA_SSSE3, "ssse3") /* SSSE3 instruction */
x86_feature(BX_ISA_SSE4_1, "sse4_1") /* SSE4_1 instruction */
x86_feature(BX_ISA_SSE4_2, "sse4_2") /* SSE4_2 instruction */
x86_feature(BX_ISA_POPCNT, "popcnt") /* POPCNT instruction */
x86_feature(BX_ISA_MONITOR_MWAIT, "mwait") /* MONITOR/MWAIT instruction */
x86_feature(BX_ISA_MONITORX_MWAITX, "mwaitx") /* MONITORX/MWAITX instruction (AMD) */
x86_feature(BX_ISA_WAITPKG, "waitpkg") /* TPAUSE/UMONITOR/UMWAIT instructions */
x86_feature(BX_ISA_VMX, "vmx") /* VMX instruction */
x86_feature(BX_ISA_SMX, "smx") /* SMX instruction */
x86_feature(BX_ISA_LONG_MODE, "longmode") /* Long Mode (x86-64) support */
x86_feature(BX_ISA_LM_LAHF_SAHF, "lm_lahf_sahf") /* Long Mode LAHF/SAHF instruction */
x86_feature(BX_ISA_NX, "nx") /* No-Execute Pages support */
x86_feature(BX_ISA_1G_PAGES, "1g_pages") /* 1Gb pages support */
x86_feature(BX_ISA_CMPXCHG16B, "cmpxhg16b") /* CMPXCHG16B instruction */
x86_feature(BX_ISA_RDTSCP, "rdtscp") /* RDTSCP instruction */
x86_feature(BX_ISA_FFXSR, "ffxsr") /* EFER.FFXSR support (AMD) */
x86_feature(BX_ISA_XSAVE, "xsave") /* XSAVE/XRSTOR extensions instruction */
x86_feature(BX_ISA_XSAVEOPT, "xsaveopt") /* XSAVEOPT instruction */
x86_feature(BX_ISA_XSAVEC, "xsavec") /* XSAVEC instruction */
x86_feature(BX_ISA_XSAVES, "xsaves") /* XSAVES instruction */
x86_feature(BX_ISA_AES_PCLMULQDQ, "aes_pclmulqdq") /* AES+PCLMULQDQ instructions */
x86_feature(BX_ISA_VAES_VPCLMULQDQ, "vaes_vpclmulqdq") /* Wide vector versions of AES+PCLMULQDQ instructions */
x86_feature(BX_ISA_MOVBE, "movbe") /* MOVBE instruction */
x86_feature(BX_ISA_FSGSBASE, "fsgsbase") /* FS/GS BASE access instruction */
x86_feature(BX_ISA_INVPCID, "invpcid") /* INVPCID instruction */
x86_feature(BX_ISA_AVX, "avx") /* AVX instruction */
x86_feature(BX_ISA_AVX2, "avx2") /* AVX2 instruction */
x86_feature(BX_ISA_AVX_F16C, "avx_f16c") /* AVX F16 convert instruction */
x86_feature(BX_ISA_AVX_FMA, "avx_fma") /* AVX FMA instruction */
x86_feature(BX_ISA_ALT_MOV_CR8, "altmovcr8") /* LOCK CR0 access CR8 (AMD) */
x86_feature(BX_ISA_SSE4A, "sse4a") /* SSE4A instruction (AMD) */
x86_feature(BX_ISA_MISALIGNED_SSE, "misaligned_sse") /* Misaligned SSE (AMD) */
x86_feature(BX_ISA_LZCNT, "lzcnt") /* LZCNT instruction */
x86_feature(BX_ISA_BMI1, "bmi1") /* BMI1 instruction */
x86_feature(BX_ISA_BMI2, "bmi2") /* BMI2 instruction */
x86_feature(BX_ISA_FMA4, "fma4") /* FMA4 instruction (AMD) */
x86_feature(BX_ISA_XOP, "xop") /* XOP instruction (AMD) */
x86_feature(BX_ISA_TBM, "tbm") /* TBM instruction (AMD) */
x86_feature(BX_ISA_SVM, "svm") /* SVM instruction (AMD) */
x86_feature(BX_ISA_RDRAND, "rdrand") /* RDRAND instruction */
x86_feature(BX_ISA_RDSEED, "rdseed") /* RDSEED instruction */
x86_feature(BX_ISA_ADX, "adx") /* ADCX/ADOX instruction */
x86_feature(BX_ISA_SMAP, "smap") /* SMAP support */
x86_feature(BX_ISA_SHA, "sha") /* SHA instruction */
x86_feature(BX_ISA_SHA512, "sha512") /* SHA-512 instruction */
x86_feature(BX_ISA_GFNI, "gfni") /* GFNI instruction */
x86_feature(BX_ISA_SM3, "sm3") /* SM3 instruction */
x86_feature(BX_ISA_SM4, "sm4") /* SM4 instruction */
#if BX_SUPPORT_EVEX
x86_feature(BX_ISA_AVX512, "avx512") /* AVX-512 instruction */
x86_feature(BX_ISA_AVX512_CD, "avx512cd") /* AVX-512 Conflict Detection instruction */
x86_feature(BX_ISA_AVX512_PF, "avx512pf") /* AVX-512 Sparse Prefetch instruction */
x86_feature(BX_ISA_AVX512_ER, "avx512er") /* AVX-512 Exponential/Reciprocal instruction */
x86_feature(BX_ISA_AVX512_DQ, "avx512dq") /* AVX-512DQ instruction */
x86_feature(BX_ISA_AVX512_BW, "avx512bw") /* AVX-512 Byte/Word instruction */
x86_feature(BX_ISA_AVX512_VBMI, "avx512vbmi") /* AVX-512 VBMI : Vector Bit Manipulation Instructions */
x86_feature(BX_ISA_AVX512_VBMI2, "avx512vbmi2") /* AVX-512 VBMI2 : Vector Bit Manipulation Instructions */
x86_feature(BX_ISA_AVX512_IFMA52, "avx512ifma52") /* AVX-512 IFMA52 Instructions */
x86_feature(BX_ISA_AVX512_VPOPCNTDQ, "avx512vpopcnt") /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
x86_feature(BX_ISA_AVX512_VNNI, "avx512vnni") /* AVX-512 VNNI Instructions */
x86_feature(BX_ISA_AVX512_BITALG, "avx512bitalg") /* AVX-512 BITALG Instructions */
x86_feature(BX_ISA_AVX512_VP2INTERSECT, "avx512vp2intersect") /* AVX-512 VP2INTERSECT Instructions */
x86_feature(BX_ISA_AVX512_BF16, "avx512bf16") /* AVX-512 BF16 Instructions */
#endif
x86_feature(BX_ISA_AVX_IFMA, "avx_ifma") /* AVX encoded IFMA Instructions */
x86_feature(BX_ISA_AVX_VNNI, "avx_vnni") /* AVX encoded VNNI Instructions */
x86_feature(BX_ISA_AVX_VNNI_INT8, "avx_vnni_int8") /* AVX encoded VNNI-INT8 Instructions */
x86_feature(BX_ISA_AVX_VNNI_INT16, "avx_vnni_int16") /* AVX encoded VNNI-INT16 Instructions */
x86_feature(BX_ISA_AVX_NE_CONVERT, "avx_ne_convert") /* AVX-NE-CONVERT Instructions */
x86_feature(BX_ISA_XAPIC, "xapic") /* XAPIC support */
x86_feature(BX_ISA_X2APIC, "x2apic") /* X2APIC support */
x86_feature(BX_ISA_XAPIC_EXT, "xapicext") /* XAPIC Extensions support (AMD) */
x86_feature(BX_ISA_PCID, "pcid") /* PCID support */
x86_feature(BX_ISA_SMEP, "smep") /* SMEP support */
x86_feature(BX_ISA_TSC_ADJUST, "tsc_adjust") /* TSC-Adjust MSR */
x86_feature(BX_ISA_TSC_DEADLINE, "tsc_deadline") /* TSC-Deadline */
x86_feature(BX_ISA_FOPCODE_DEPRECATION, "fopcode_deprecation") /* FOPCODE Deprecation - FOPCODE update on unmasked x87 exception only */
x86_feature(BX_ISA_FCS_FDS_DEPRECATION, "fcs_fds_deprecation") /* FCS/FDS Deprecation */
x86_feature(BX_ISA_FDP_DEPRECATION, "fdp_deprecation") /* FDP Deprecation - FDP update on unmasked x87 exception only */
x86_feature(BX_ISA_PKU, "pku") /* User-Mode Protection Keys */
x86_feature(BX_ISA_PKS, "pks") /* Supervisor-Mode Protection Keys */
x86_feature(BX_ISA_UMIP, "umip") /* User-Mode Instructions Prevention */
x86_feature(BX_ISA_RDPID, "rdpid") /* RDPID Support */
x86_feature(BX_ISA_TCE, "tce") /* Translation Cache Extensions (TCE) support (AMD) */
x86_feature(BX_ISA_CLZERO, "clzero") /* CLZERO instruction support (AMD) */
x86_feature(BX_ISA_SCA_MITIGATIONS, "sca_mitigations") /* Report SCA Mitigations in CPUID */
x86_feature(BX_ISA_CET, "cet") /* Control Flow Enforcement */
x86_feature(BX_ISA_WRMSRNS, "wrmsrns") /* Non-Serializing version of WRMSR */
x86_feature(BX_ISA_CMPCCXADD, "cmpccxadd") /* CMPccXADD instructions */
x86_feature(BX_ISA_SERIALIZE, "serialize") /* SERIALIZE instruction */
x86_feature(BX_ISA_LASS, "lass") /* Linear Address Space Separation support */
#endif

1
bochs/cpu/generic_cpuid.cc
View File

@ -589,7 +589,6 @@ void bx_generic_cpuid_t::init_cpu_extensions_bitmask(void)
#if BX_SUPPORT_EVEX
case BX_CPUID_SUPPORT_AVX512:
enable_cpu_extension(BX_ISA_AVX512);
enable_cpu_extension(BX_ISA_AVX512_VL);
enable_cpu_extension(BX_ISA_AVX512_BW);
enable_cpu_extension(BX_ISA_AVX512_DQ);
enable_cpu_extension(BX_ISA_AVX512_CD);