1007 lines
32 KiB
C++
1007 lines
32 KiB
C++
/////////////////////////////////////////////////////////////////////////
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// $Id$
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2014-2020 Stanislav Shwartsman
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// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
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//
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// This library is free software; you can redistribute it and/or
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// modify it under the terms of the GNU Lesser General Public
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// License as published by the Free Software Foundation; either
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// version 2 of the License, or (at your option) any later version.
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//
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// This library is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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// Lesser General Public License for more details.
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//
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// You should have received a copy of the GNU Lesser General Public
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// License along with this library; if not, write to the Free Software
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// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
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//
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/////////////////////////////////////////////////////////////////////////
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#include "bochs.h"
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#include "gui/siminterface.h"
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#include "cpu.h"
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#include "param_names.h"
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#include "cpuid.h"
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static const char *cpu_feature_name[] =
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{
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"386ni", // BX_ISA_386
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"x87", // BX_ISA_X87
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"486ni", // BX_ISA_486
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"pentium_ni", // BX_ISA_PENTIUM
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"p6ni", // BX_ISA_P6
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"mmx", // BX_ISA_MMX
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"3dnow!", // BX_ISA_3DNOW
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"debugext", // BX_ISA_DEBUG_EXTENSIONS
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"vme", // BX_ISA_VME
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"pse", // BX_ISA_PSE
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"pae", // BX_ISA_PAE
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"pge", // BX_ISA_PGE
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"pse36", // BX_ISA_PSE36
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"mtrr", // BX_ISA_MTRR
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"pat", // BX_ISA_PAT
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"legacy_syscall_sysret", // BX_ISA_SYSCALL_SYSRET_LEGACY
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"sysenter_sysexit", // BX_ISA_SYSENTER_SYSEXIT
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"clflush", // BX_ISA_CLFLUSH
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"clflushopt", // BX_ISA_CLFLUSHOPT
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"clwb", // BX_ISA_CLWB
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"cldemote", // BX_ISA_CLDEMOTE
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"sse", // BX_ISA_SSE
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"sse2", // BX_ISA_SSE2
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"sse3", // BX_ISA_SSE3
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"ssse3", // BX_ISA_SSSE3
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"sse4_1", // BX_ISA_SSE4_1
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"sse4_2", // BX_ISA_SSE4_2
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"popcnt", // BX_ISA_POPCNT
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"mwait", // BX_ISA_MONITOR_MWAIT
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"mwaitx", // BX_ISA_MONITORX_MWAITX
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"waitpkg", // BX_ISA_WAITPKG
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"vmx", // BX_ISA_VMX
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"smx", // BX_ISA_SMX
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"longmode", // BX_ISA_LONG_MODE
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"lm_lahf_sahf", // BX_ISA_LM_LAHF_SAHF
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"nx", // BX_ISA_NX
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"1g_pages", // BX_ISA_1G_PAGES
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"cmpxhg16b", // BX_ISA_CMPXCHG16B
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"rdtscp", // BX_ISA_RDTSCP
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"ffxsr", // BX_ISA_FFXSR
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"xsave", // BX_ISA_XSAVE
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"xsaveopt", // BX_ISA_XSAVEOPT
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"xsavec", // BX_ISA_XSAVEC
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"xsaves", // BX_ISA_XSAVES
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"aes_pclmulqdq", // BX_ISA_AES_PCLMULQDQ
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"vaes_vpclmulqdq", // BX_ISA_VAES_VPCLMULQDQ
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"movbe", // BX_ISA_MOVBE
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"fsgsbase", // BX_ISA_FSGSBASE
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"invpcid", // BX_ISA_INVPCID
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"avx", // BX_ISA_AVX
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"avx2", // BX_ISA_AVX2
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"avx_f16c", // BX_ISA_AVX_F16C
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"avx_fma", // BX_ISA_AVX_FMA
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"altmovcr8", // BX_ISA_ALT_MOV_CR8
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"sse4a", // BX_ISA_SSE4A
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"misaligned_sse", // BX_ISA_MISALIGNED_SSE
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"lzcnt", // BX_ISA_LZCNT
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"bmi1", // BX_ISA_BMI1
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"bmi2", // BX_ISA_BMI2
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"fma4", // BX_ISA_FMA4
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"xop", // BX_ISA_XOP
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"tbm", // BX_ISA_TBM
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"svm", // BX_ISA_SVM
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"rdrand", // BX_ISA_RDRAND
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"adx", // BX_ISA_ADX
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"smap", // BX_ISA_SMAP
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"rdseed", // BX_ISA_RDSEED
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"sha", // BX_ISA_SHA
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"gfni", // BX_ISA_GFNI
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"avx512", // BX_ISA_AVX512
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"avx512cd", // BX_ISA_AVX512_CD
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"avx512pf", // BX_ISA_AVX512_PF
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"avx512er", // BX_ISA_AVX512_ER
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"avx512dq", // BX_ISA_AVX512_DQ
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"avx512bw", // BX_ISA_AVX512_BW
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"avx512vl", // BX_ISA_AVX512_VL
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"avx512vbmi", // BX_ISA_AVX512_VBMI
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"avx512vbmi2", // BX_ISA_AVX512_VBMI2
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"avx512ifma52", // BX_ISA_AVX512_IFMA52
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"avx512vpopcnt", // BX_ISA_AVX512_VPOPCNTDQ
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"avx512vnni", // BX_ISA_AVX512_VNNI
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"avx512bitalg", // BX_ISA_AVX512_BITALG
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"avx512vp2intersect", // BX_ISA_AVX512_VP2INTERSECT
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"avx_vnni", // BX_ISA_AVX_VNNI
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"avx_ifma", // BX_ISA_AVX_IFMA
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"avx_vnni_int8", // BX_ISA_AVX_VNNI_INT8
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"xapic", // BX_ISA_XAPIC
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"x2apic", // BX_ISA_X2APIC
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"xapicext", // BX_ISA_XAPICEXT
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"pcid", // BX_ISA_PCID
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"smep", // BX_ISA_SMEP
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"tsc_adjust", // BX_ISA_TSC_ADJUST
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"tsc_deadline", // BX_ISA_TSC_DEADLINE
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"fopcode_deprecation", // BX_ISA_FOPCODE_DEPRECATION
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"fcs_fds_deprecation", // BX_ISA_FCS_FDS_DEPRECATION
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"fdp_deprecation", // BX_ISA_FDP_DEPRECATION
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"pku", // BX_ISA_PKU
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"pks", // BX_ISA_PKS
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"umip", // BX_ISA_UMIP
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"rdpid", // BX_ISA_RDPID
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"tce", // BX_ISA_TCE
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"clzero", // BX_ISA_CLZERO
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"sca_mitigations", // BX_ISA_SCA_MITIGATIONS
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"cet", // BX_ISA_CET
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"wrmsrns", // BX_ISA_WRMSRNS
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"cmpccxadd", // BX_ISA_CMPCCXADD
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};
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const char *get_cpu_feature_name(unsigned feature) { return cpu_feature_name[feature]; }
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#define LOG_THIS cpu->
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bx_cpuid_t::bx_cpuid_t(BX_CPU_C *_cpu): cpu(_cpu)
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{
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init();
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}
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#if BX_SUPPORT_VMX
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bx_cpuid_t::bx_cpuid_t(BX_CPU_C *_cpu, Bit32u vmcs_revision):
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cpu(_cpu), vmcs_map(vmcs_revision)
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{
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init();
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}
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bx_cpuid_t::bx_cpuid_t(BX_CPU_C *_cpu, Bit32u vmcs_revision, const char *filename):
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cpu(_cpu), vmcs_map(vmcs_revision, filename)
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{
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init();
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}
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#endif
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void bx_cpuid_t::init()
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{
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#if BX_SUPPORT_SMP
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nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
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ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get();
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nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get();
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#else
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nthreads = 1;
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ncores = 1;
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nprocessors = 1;
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#endif
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for (unsigned n=0; n < BX_ISA_EXTENSIONS_ARRAY_SIZE; n++)
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ia_extensions_bitmask[n] = 0;
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// every cpu supported by Bochs support all 386 and earlier instructions
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ia_extensions_bitmask[0] = (1 << BX_ISA_386);
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}
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#if BX_SUPPORT_APIC
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BX_CPP_INLINE static Bit32u ilog2(Bit32u x)
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{
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Bit32u count = 0;
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while(x>>=1) count++;
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return count;
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}
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// leaf 0x0000000B //
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void bx_cpuid_t::get_std_cpuid_extended_topology_leaf(Bit32u subfunction, cpuid_function_t *leaf) const
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{
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// CPUID function 0x0000000B - Extended Topology Leaf
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = subfunction;
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leaf->edx = cpu->get_apic_id();
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#if BX_SUPPORT_SMP
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switch(subfunction) {
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case 0:
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if (nthreads > 1) {
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leaf->eax = ilog2(nthreads-1)+1;
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leaf->ebx = nthreads;
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leaf->ecx |= (1<<8);
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}
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else if (ncores > 1) {
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leaf->eax = ilog2(ncores-1)+1;
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leaf->ebx = ncores;
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leaf->ecx |= (2<<8);
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}
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else if (nprocessors > 1) {
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leaf->eax = ilog2(nprocessors-1)+1;
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leaf->ebx = nprocessors;
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}
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else {
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leaf->eax = 1;
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leaf->ebx = 1; // number of logical CPUs at this level
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}
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break;
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case 1:
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if (nthreads > 1) {
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if (ncores > 1) {
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leaf->eax = ilog2(ncores-1)+1;
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leaf->ebx = ncores;
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leaf->ecx |= (2<<8);
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}
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else if (nprocessors > 1) {
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leaf->eax = ilog2(nprocessors-1)+1;
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leaf->ebx = nprocessors;
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}
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}
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else if (ncores > 1) {
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if (nprocessors > 1) {
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leaf->eax = ilog2(nprocessors-1)+1;
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leaf->ebx = nprocessors;
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}
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}
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break;
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case 2:
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if (nthreads > 1) {
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if (nprocessors > 1) {
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leaf->eax = ilog2(nprocessors-1)+1;
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leaf->ebx = nprocessors;
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}
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}
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break;
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default:
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break;
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}
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#endif
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}
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#endif
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#if BX_CPU_LEVEL >= 6
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void bx_cpuid_t::get_std_cpuid_xsave_leaf(Bit32u subfunction, cpuid_function_t *leaf) const
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{
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leaf->eax = 0;
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leaf->ebx = 0;
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leaf->ecx = 0;
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leaf->edx = 0;
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if (is_cpu_extension_supported(BX_ISA_XSAVE))
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{
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switch(subfunction) {
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case 0:
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// EAX - valid bits of XCR0 (lower part)
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// EBX - Maximum size (in bytes) required by enabled features
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// ECX - Maximum size (in bytes) required by CPU supported features
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// EDX - valid bits of XCR0 (upper part)
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leaf->eax = cpu->xcr0_suppmask;
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leaf->ebx = 512+64;
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#if BX_SUPPORT_AVX
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if (cpu->xcr0.get_YMM())
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leaf->ebx = XSAVE_YMM_STATE_OFFSET + XSAVE_YMM_STATE_LEN;
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#endif
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#if BX_SUPPORT_EVEX
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if (cpu->xcr0.get_OPMASK())
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leaf->ebx = XSAVE_OPMASK_STATE_OFFSET + XSAVE_OPMASK_STATE_LEN;
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if (cpu->xcr0.get_ZMM_HI256())
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leaf->ebx = XSAVE_ZMM_HI256_STATE_OFFSET + XSAVE_ZMM_HI256_STATE_LEN;
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if (cpu->xcr0.get_HI_ZMM())
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leaf->ebx = XSAVE_HI_ZMM_STATE_OFFSET + XSAVE_HI_ZMM_STATE_LEN;
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#endif
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#if BX_SUPPORT_PKEYS
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if (cpu->xcr0.get_PKRU())
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leaf->ebx = XSAVE_PKRU_STATE_OFFSET + XSAVE_PKRU_STATE_LEN;
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#endif
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leaf->ecx = 512+64;
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#if BX_SUPPORT_AVX
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if (cpu->xcr0_suppmask & BX_XCR0_YMM_MASK)
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leaf->ecx = XSAVE_YMM_STATE_OFFSET + XSAVE_YMM_STATE_LEN;
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#endif
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#if BX_SUPPORT_EVEX
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if (cpu->xcr0_suppmask & BX_XCR0_OPMASK_MASK)
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leaf->ecx = XSAVE_OPMASK_STATE_OFFSET + XSAVE_OPMASK_STATE_LEN;
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if (cpu->xcr0_suppmask & BX_XCR0_ZMM_HI256_MASK)
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leaf->ecx = XSAVE_ZMM_HI256_STATE_OFFSET + XSAVE_ZMM_HI256_STATE_LEN;
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if (cpu->xcr0_suppmask & BX_XCR0_HI_ZMM_MASK)
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leaf->ecx = XSAVE_HI_ZMM_STATE_OFFSET + XSAVE_HI_ZMM_STATE_LEN;
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#endif
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#if BX_SUPPORT_PKEYS
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if (cpu->xcr0_suppmask & BX_XCR0_PKRU_MASK)
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leaf->ecx = XSAVE_PKRU_STATE_OFFSET + XSAVE_PKRU_STATE_LEN;
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#endif
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leaf->edx = 0;
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break;
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case 1:
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// EAX[0] - support for the XSAVEOPT instruction
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// EAX[1] - support for compaction extensions to the XSAVE feature set
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// EAX[2] - support for execution of XGETBV with ECX = 1
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// EAX[3] - support for XSAVES, XRSTORS, and the IA32_XSS MSR
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leaf->eax = 0;
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if (is_cpu_extension_supported(BX_ISA_XSAVEOPT))
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leaf->eax |= 0x1;
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if (is_cpu_extension_supported(BX_ISA_XSAVEC))
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leaf->eax |= (1<<1) | (1<<2);
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if (is_cpu_extension_supported(BX_ISA_XSAVES))
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leaf->eax |= (1<<3);
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// EBX[31:00] - The size (in bytes) of the XSAVE area containing all states enabled by (XCRO | IA32_XSS)
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leaf->ebx = 0;
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if (is_cpu_extension_supported(BX_ISA_XSAVES)) {
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xcr0_t xcr0_xss = cpu->xcr0;
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xcr0_xss.val32 |= cpu->msr.ia32_xss;
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#if BX_SUPPORT_AVX
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if (xcr0_xss.get_YMM())
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leaf->ebx = XSAVE_YMM_STATE_OFFSET + XSAVE_YMM_STATE_LEN;
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#endif
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#if BX_SUPPORT_EVEX
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if (xcr0_xss.get_OPMASK())
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leaf->ebx = XSAVE_OPMASK_STATE_OFFSET + XSAVE_OPMASK_STATE_LEN;
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if (xcr0_xss.get_ZMM_HI256())
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leaf->ebx = XSAVE_ZMM_HI256_STATE_OFFSET + XSAVE_ZMM_HI256_STATE_LEN;
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if (xcr0_xss.get_HI_ZMM())
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leaf->ebx = XSAVE_HI_ZMM_STATE_OFFSET + XSAVE_HI_ZMM_STATE_LEN;
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#endif
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#if BX_SUPPORT_PKEYS
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if (xcr0_xss.get_PKRU())
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leaf->ebx = XSAVE_PKRU_STATE_OFFSET + XSAVE_PKRU_STATE_LEN;
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#endif
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}
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// ECX[31:0] - Reports the supported bits of the lower 32 bits of the IA32_XSS MSR.
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// IA32_XSS[n] can be set to 1 only if ECX[n] is 1
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// EDX[31:0] - Reports the supported bits of the upper 32 bits of the IA32_XSS MSR.
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// IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1
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leaf->ecx = 0;
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#if BX_SUPPPORT_CET
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leaf->ecx |= BX_XCR0_CET_U_MASK | BX_XCR0_CET_S_MASK;
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#endif
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leaf->edx = 0;
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break;
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#if BX_SUPPORT_AVX
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case 2: // YMM leaf
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if (cpu->xcr0_suppmask & BX_XCR0_YMM_MASK) {
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leaf->eax = XSAVE_YMM_STATE_LEN;
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leaf->ebx = XSAVE_YMM_STATE_OFFSET;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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break;
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#endif
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case 3: // MPX leafs (BNDREGS, BNDCFG)
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case 4:
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break;
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#if BX_SUPPORT_EVEX
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case 5: // OPMASK leaf
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if (cpu->xcr0_suppmask & BX_XCR0_OPMASK_MASK) {
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leaf->eax = XSAVE_OPMASK_STATE_LEN;
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leaf->ebx = XSAVE_OPMASK_STATE_OFFSET;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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break;
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case 6: // ZMM Hi256 leaf
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if (cpu->xcr0_suppmask & BX_XCR0_ZMM_HI256_MASK) {
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leaf->eax = XSAVE_ZMM_HI256_STATE_LEN;
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leaf->ebx = XSAVE_ZMM_HI256_STATE_OFFSET;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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break;
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case 7: // HI_ZMM leaf
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if (cpu->xcr0_suppmask & BX_XCR0_HI_ZMM_MASK) {
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leaf->eax = XSAVE_HI_ZMM_STATE_LEN;
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leaf->ebx = XSAVE_HI_ZMM_STATE_OFFSET;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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break;
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#endif
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case 8: // Processor trace leaf
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break;
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#if BX_SUPPPORT_PKEYS
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case 9: // Protection keys
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if (cpu->xcr0_suppmask & BX_XCR0_PKRU_MASK) {
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leaf->eax = XSAVE_PKRU_STATE_LEN;
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leaf->ebx = XSAVE_PKRU_STATE_OFFSET;
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leaf->ecx = 0;
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leaf->edx = 0;
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}
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break;
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#endif
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#if BX_SUPPPORT_CET
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case 10:
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if (cpu->xcr0_suppmask & BX_XCR0_CET_U_MASK) {
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leaf->eax = XSAVE_CET_U_STATE_LEN;
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leaf->ebx = 0; // doesn't map to a valid bit in XCR0 register
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leaf->ecx = 1; // managed through IA32_XSS register
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leaf->edx = 0;
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}
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break;
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case 11:
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if (cpu->xcr0_suppmask & BX_XCR0_CET_S_MASK) {
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leaf->eax = XSAVE_CET_S_STATE_LEN;
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leaf->ebx = 0; // doesn't map to a valid bit in XCR0 register
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leaf->ecx = 1; // managed through IA32_XSS register
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|
leaf->edx = 0;
|
|
}
|
|
break;
|
|
#endif
|
|
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
void bx_cpuid_t::get_leaf_0(unsigned max_leaf, const char *vendor_string, cpuid_function_t *leaf, unsigned limited_max_leaf) const
|
|
{
|
|
// EAX: highest function understood by CPUID
|
|
// EBX: vendor ID string
|
|
// EDX: vendor ID string
|
|
// ECX: vendor ID string
|
|
if (max_leaf < 0x80000000 && max_leaf > 0x2) {
|
|
// do not limit extended CPUID leafs
|
|
static bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get();
|
|
if (cpuid_limit_winnt)
|
|
max_leaf = (limited_max_leaf < 0x02) ? limited_max_leaf : 0x02;
|
|
}
|
|
leaf->eax = max_leaf;
|
|
|
|
if (vendor_string == NULL) {
|
|
leaf->ebx = 0;
|
|
leaf->ecx = 0; // Reserved
|
|
leaf->edx = 0;
|
|
return;
|
|
}
|
|
|
|
// CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...)
|
|
memcpy(&(leaf->ebx), vendor_string, 4);
|
|
memcpy(&(leaf->edx), vendor_string + 4, 4);
|
|
memcpy(&(leaf->ecx), vendor_string + 8, 4);
|
|
#ifdef BX_BIG_ENDIAN
|
|
leaf->ebx = bx_bswap32(leaf->ebx);
|
|
leaf->ecx = bx_bswap32(leaf->ecx);
|
|
leaf->edx = bx_bswap32(leaf->edx);
|
|
#endif
|
|
}
|
|
|
|
void bx_cpuid_t::get_ext_cpuid_brand_string_leaf(const char *brand_string, Bit32u function, cpuid_function_t *leaf) const
|
|
{
|
|
switch(function) {
|
|
case 0x80000002:
|
|
memcpy(&(leaf->eax), brand_string , 4);
|
|
memcpy(&(leaf->ebx), brand_string + 4, 4);
|
|
memcpy(&(leaf->ecx), brand_string + 8, 4);
|
|
memcpy(&(leaf->edx), brand_string + 12, 4);
|
|
break;
|
|
case 0x80000003:
|
|
memcpy(&(leaf->eax), brand_string + 16, 4);
|
|
memcpy(&(leaf->ebx), brand_string + 20, 4);
|
|
memcpy(&(leaf->ecx), brand_string + 24, 4);
|
|
memcpy(&(leaf->edx), brand_string + 28, 4);
|
|
break;
|
|
case 0x80000004:
|
|
memcpy(&(leaf->eax), brand_string + 32, 4);
|
|
memcpy(&(leaf->ebx), brand_string + 36, 4);
|
|
memcpy(&(leaf->ecx), brand_string + 40, 4);
|
|
memcpy(&(leaf->edx), brand_string + 44, 4);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
#ifdef BX_BIG_ENDIAN
|
|
leaf->eax = bx_bswap32(leaf->eax);
|
|
leaf->ebx = bx_bswap32(leaf->ebx);
|
|
leaf->ecx = bx_bswap32(leaf->ecx);
|
|
leaf->edx = bx_bswap32(leaf->edx);
|
|
#endif
|
|
}
|
|
|
|
// leaf 0x00000001 - ECX
|
|
Bit32u bx_cpuid_t::get_std_cpuid_leaf_1_ecx(Bit32u extra) const
|
|
{
|
|
Bit32u ecx = extra;
|
|
|
|
// [0:0] SSE3: SSE3 Instructions
|
|
if (is_cpu_extension_supported(BX_ISA_SSE3))
|
|
ecx |= BX_CPUID_EXT_SSE3;
|
|
|
|
// [1:1] PCLMULQDQ Instruction support
|
|
if (is_cpu_extension_supported(BX_ISA_AES_PCLMULQDQ))
|
|
ecx |= BX_CPUID_EXT_PCLMULQDQ;
|
|
|
|
// [2:2] DTES64: 64-bit DS area - not supported, could be enable through extra
|
|
|
|
// [3:3] MONITOR/MWAIT support
|
|
#if BX_SUPPORT_MONITOR_MWAIT
|
|
if (is_cpu_extension_supported(BX_ISA_MONITOR_MWAIT))
|
|
ecx |= BX_CPUID_EXT_MONITOR_MWAIT;
|
|
#endif
|
|
|
|
// [4:4] DS-CPL: CPL qualified debug store - not supported, could be enable through extra
|
|
|
|
// [5:5] VMX: Virtual Machine Technology
|
|
#if BX_SUPPORT_VMX >= 2
|
|
if (is_cpu_extension_supported(BX_ISA_VMX))
|
|
ecx |= BX_CPUID_EXT_VMX;
|
|
#endif
|
|
|
|
// [6:6] SMX: Secure Virtual Machine Technology - not supported
|
|
// [7:7] EST: Enhanced Intel SpeedStep Technology - not supported, could be enabled through extra
|
|
// [8:8] TM2: Thermal Monitor 2 - not supported, could be enabled through extra
|
|
|
|
// [9:9] SSSE3: SSSE3 Instructions
|
|
if (is_cpu_extension_supported(BX_ISA_SSSE3))
|
|
ecx |= BX_CPUID_EXT_SSSE3;
|
|
|
|
// [10:10] CNXT-ID: L1 context ID - not supported, could be enabled through extra
|
|
// [11:11] reserved
|
|
|
|
// [12:12] FMA Instructions support
|
|
if (is_cpu_extension_supported(BX_ISA_AVX_FMA))
|
|
ecx |= BX_CPUID_EXT_FMA;
|
|
|
|
// [13:13] CMPXCHG16B: CMPXCHG16B instruction support
|
|
if (is_cpu_extension_supported(BX_ISA_CMPXCHG16B))
|
|
ecx |= BX_CPUID_EXT_CMPXCHG16B;
|
|
|
|
// [14:14] xTPR update control - not supported, could be enabled through extra
|
|
// [15:15] PDCM - Perfmon and Debug Capability MSR - not supported, could be enabled through extra
|
|
// [16:16] reserved
|
|
|
|
// [17:17] PCID: Process Context Identifiers
|
|
if (is_cpu_extension_supported(BX_ISA_PCID))
|
|
ecx |= BX_CPUID_EXT_PCID;
|
|
|
|
// [18:18] DCA - Direct Cache Access - not supported, could be enabled through extra
|
|
|
|
// [19:19] SSE4.1 Instructions
|
|
if (is_cpu_extension_supported(BX_ISA_SSE4_1))
|
|
ecx |= BX_CPUID_EXT_SSE4_1;
|
|
|
|
// [20:20] SSE4.2 Instructions
|
|
if (is_cpu_extension_supported(BX_ISA_SSE4_2))
|
|
ecx |= BX_CPUID_EXT_SSE4_2;
|
|
|
|
// [21:21] X2APIC
|
|
if (is_cpu_extension_supported(BX_ISA_X2APIC))
|
|
ecx |= BX_CPUID_EXT_X2APIC;
|
|
|
|
// [22:22] MOVBE instruction
|
|
if (is_cpu_extension_supported(BX_ISA_MOVBE))
|
|
ecx |= BX_CPUID_EXT_MOVBE;
|
|
|
|
// [23:23] POPCNT instruction
|
|
if (is_cpu_extension_supported(BX_ISA_POPCNT))
|
|
ecx |= BX_CPUID_EXT_POPCNT;
|
|
|
|
// [24:24] TSC Deadline
|
|
if (is_cpu_extension_supported(BX_ISA_TSC_DEADLINE))
|
|
ecx |= BX_CPUID_EXT_TSC_DEADLINE;
|
|
|
|
// [25:25] AES Instructions
|
|
if (is_cpu_extension_supported(BX_ISA_AES_PCLMULQDQ))
|
|
ecx |= BX_CPUID_EXT_AES;
|
|
|
|
// [26:26] XSAVE extensions support
|
|
if (is_cpu_extension_supported(BX_ISA_XSAVE))
|
|
ecx |= BX_CPUID_EXT_XSAVE;
|
|
|
|
// [27:27] OSXSAVE support
|
|
if (cpu->cr4.get_OSXSAVE())
|
|
ecx |= BX_CPUID_EXT_OSXSAVE;
|
|
|
|
// [28:28] AVX extensions support
|
|
if (is_cpu_extension_supported(BX_ISA_AVX))
|
|
ecx |= BX_CPUID_EXT_AVX;
|
|
|
|
// [29:29] AVX F16C - Float16 conversion support
|
|
if (is_cpu_extension_supported(BX_ISA_AVX_F16C))
|
|
ecx |= BX_CPUID_EXT_AVX_F16C;
|
|
|
|
// [30:30] RDRAND instruction
|
|
if (is_cpu_extension_supported(BX_ISA_RDRAND))
|
|
ecx |= BX_CPUID_EXT_RDRAND;
|
|
|
|
// [31:31] reserved
|
|
|
|
return ecx;
|
|
}
|
|
|
|
// leaf 0x00000001 - EDX[18:12,10:0]
|
|
Bit32u bx_cpuid_t::get_std_cpuid_leaf_1_edx_common(Bit32u extra) const
|
|
{
|
|
Bit32u edx = 0;
|
|
|
|
// [0:0] FPU on chip
|
|
if (is_cpu_extension_supported(BX_ISA_X87))
|
|
edx |= BX_CPUID_STD_X87;
|
|
|
|
// [1:1] VME: Virtual-8086 Mode enhancements
|
|
if (is_cpu_extension_supported(BX_ISA_VME))
|
|
edx |= BX_CPUID_STD_VME;
|
|
|
|
// [2:2] DE: Debug Extensions (I/O breakpoints)
|
|
if (is_cpu_extension_supported(BX_ISA_DEBUG_EXTENSIONS))
|
|
edx |= BX_CPUID_STD_DEBUG_EXTENSIONS;
|
|
|
|
// [3:3] PSE: Page Size Extensions
|
|
if (is_cpu_extension_supported(BX_ISA_PSE))
|
|
edx |= BX_CPUID_STD_PSE;
|
|
|
|
// [4:4] TSC: Time Stamp Counter
|
|
if (is_cpu_extension_supported(BX_ISA_PENTIUM))
|
|
edx |= BX_CPUID_STD_TSC;
|
|
|
|
// [5:5] MSR: RDMSR and WRMSR support
|
|
if (is_cpu_extension_supported(BX_ISA_PENTIUM))
|
|
edx |= BX_CPUID_STD_MSR;
|
|
|
|
// [6:6] PAE: Physical Address Extensions
|
|
if (is_cpu_extension_supported(BX_ISA_PAE))
|
|
edx |= BX_CPUID_STD_PAE;
|
|
|
|
// [7:7] MCE: Machine Check Exception - not implemented, could be enabled through extra
|
|
|
|
// [8:8] CXS: CMPXCHG8B instruction
|
|
if (is_cpu_extension_supported(BX_ISA_PENTIUM))
|
|
edx |= BX_CPUID_STD_CMPXCHG8B;
|
|
|
|
// [9:9] APIC: APIC on Chip
|
|
#if BX_SUPPORT_APIC
|
|
if (is_cpu_extension_supported(BX_ISA_XAPIC)) {
|
|
// if MSR_APICBASE APIC Global Enable bit has been cleared,
|
|
// the CPUID feature flag for the APIC is set to 0.
|
|
if (cpu->msr.apicbase & 0x800)
|
|
edx |= BX_CPUID_STD_APIC; // APIC on chip
|
|
}
|
|
#endif
|
|
|
|
// [10:10] Reserved
|
|
|
|
// [11:11] Not common between Intel and AMD
|
|
|
|
// [12:12] MTRR: Memory Type Range Reg
|
|
if (is_cpu_extension_supported(BX_ISA_MTRR))
|
|
edx |= BX_CPUID_STD_MTRR;
|
|
|
|
// [13:13] PGE/PTE Global Bit
|
|
if (is_cpu_extension_supported(BX_ISA_PGE))
|
|
edx |= BX_CPUID_STD_GLOBAL_PAGES;
|
|
|
|
// [14:14] MCA: Machine Check Architecture - not implemented, could be enabled through extra
|
|
|
|
// [15:15] CMOV: Cond Mov/Cmp Instructions
|
|
if (is_cpu_extension_supported(BX_ISA_P6))
|
|
edx |= BX_CPUID_STD_CMOV;
|
|
|
|
// [16:16] PAT: Page Attribute Table
|
|
if (is_cpu_extension_supported(BX_ISA_PAT))
|
|
edx |= BX_CPUID_STD_PAT;
|
|
|
|
#if BX_PHY_ADDRESS_LONG
|
|
// [17:17] PSE-36: Physical Address Extensions
|
|
if (is_cpu_extension_supported(BX_ISA_PSE36))
|
|
edx |= BX_CPUID_STD_PSE36;
|
|
#endif
|
|
|
|
// [18:18] PSN: Processor Serial Number - could be enabled through extra
|
|
|
|
return edx;
|
|
}
|
|
|
|
// leaf 0x00000007 - EBX
|
|
Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_ebx(Bit32u extra) const
|
|
{
|
|
Bit32u ebx = extra;
|
|
|
|
// [0:0] FS/GS BASE access instructions
|
|
if (is_cpu_extension_supported(BX_ISA_FSGSBASE))
|
|
ebx |= BX_CPUID_EXT3_FSGSBASE;
|
|
|
|
// [1:1] Support for IA32_TSC_ADJUST MSR
|
|
if (is_cpu_extension_supported(BX_ISA_TSC_ADJUST))
|
|
ebx |= BX_CPUID_EXT3_TSC_ADJUST;
|
|
|
|
// [2:2] SGX: Intel Software Guard Extensions - not supported
|
|
|
|
// [3:3] BMI1: Advanced Bit Manipulation Extensions
|
|
if (is_cpu_extension_supported(BX_ISA_BMI1))
|
|
ebx |= BX_CPUID_EXT3_BMI1;
|
|
|
|
// [4:4] HLE: Hardware Lock Elision - not supported
|
|
|
|
// [5:5] AVX2
|
|
if (is_cpu_extension_supported(BX_ISA_AVX2))
|
|
ebx |= BX_CPUID_EXT3_AVX2;
|
|
|
|
// [6:6] FDP Deprecation
|
|
if (is_cpu_extension_supported(BX_ISA_FDP_DEPRECATION))
|
|
ebx |= BX_CPUID_EXT3_FDP_DEPRECATION;
|
|
|
|
// [7:7] SMEP: Supervisor Mode Execution Protection
|
|
if (is_cpu_extension_supported(BX_ISA_SMEP))
|
|
ebx |= BX_CPUID_EXT3_SMEP;
|
|
|
|
// [8:8] BMI2: Advanced Bit Manipulation Extensions
|
|
if (is_cpu_extension_supported(BX_ISA_BMI2))
|
|
ebx |= BX_CPUID_EXT3_BMI2;
|
|
|
|
// [9:9] Support for Enhanced REP MOVSB/STOSB - no special emulation required, could be enabled through extra
|
|
|
|
// [10:10] Support for INVPCID instruction
|
|
if (is_cpu_extension_supported(BX_ISA_INVPCID))
|
|
ebx |= BX_CPUID_EXT3_INVPCID;
|
|
|
|
// [11:11] RTM: Restricted Transactional Memory - not supported
|
|
// [12:12] Supports Platform Quality of Service Monitoring (PQM) capability - not supported
|
|
|
|
// [13:13] Deprecates FPU CS and FPU DS values
|
|
if (is_cpu_extension_supported(BX_ISA_FCS_FDS_DEPRECATION))
|
|
ebx |= BX_CPUID_EXT3_DEPRECATE_FCS_FDS;
|
|
|
|
// [14:14] Intel Memory Protection Extensions - not supported
|
|
// [15:15] Supports Platform Quality of Service Enforcement (PQE) capability - not supported
|
|
|
|
// [16:16] AVX512F instructions support
|
|
// [17:17] AVX512DQ instructions support
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
ebx |= BX_CPUID_EXT3_AVX512F;
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_DQ))
|
|
ebx |= BX_CPUID_EXT3_AVX512DQ;
|
|
}
|
|
#endif
|
|
|
|
// [18:18] RDSEED instruction support
|
|
if (is_cpu_extension_supported(BX_ISA_RDSEED))
|
|
ebx |= BX_CPUID_EXT3_RDSEED;
|
|
|
|
// [19:19] ADCX/ADOX instructions support
|
|
if (is_cpu_extension_supported(BX_ISA_ADX))
|
|
ebx |= BX_CPUID_EXT3_ADX;
|
|
|
|
// [20:20] SMAP: Supervisor Mode Access Prevention
|
|
if (is_cpu_extension_supported(BX_ISA_SMAP))
|
|
ebx |= BX_CPUID_EXT3_SMAP;
|
|
|
|
// [22:21] AVX512IFMA52 instructions support
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_IFMA52))
|
|
ebx |= BX_CPUID_EXT3_AVX512IFMA52;
|
|
}
|
|
#endif
|
|
|
|
// [22:22] reserved
|
|
|
|
// [23:23] CLFLUSHOPT instruction
|
|
// [24:24] CLWB instruction
|
|
if (is_cpu_extension_supported(BX_ISA_CLFLUSHOPT))
|
|
ebx |= BX_CPUID_EXT3_CLFLUSHOPT;
|
|
if (is_cpu_extension_supported(BX_ISA_CLWB))
|
|
ebx |= BX_CPUID_EXT3_CLWB;
|
|
|
|
// [25:25] Intel Processor Trace - not supported
|
|
// [26:26] AVX512PF instructions support - not supported
|
|
// [27:27] AVX512ER instructions support - not supported
|
|
// [28:28] AVX512CD instructions support
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_CD))
|
|
ebx |= BX_CPUID_EXT3_AVX512CD;
|
|
}
|
|
#endif
|
|
|
|
// [29:29] SHA instructions support
|
|
if (is_cpu_extension_supported(BX_ISA_SHA))
|
|
ebx |= BX_CPUID_EXT3_SHA;
|
|
|
|
// [30:30] AVX512BW instructions support
|
|
// [31:31] AVX512VL variable vector length support
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_BW))
|
|
ebx |= BX_CPUID_EXT3_AVX512BW;
|
|
ebx |= BX_CPUID_EXT3_AVX512VL;
|
|
}
|
|
|
|
return ebx;
|
|
}
|
|
|
|
// leaf 0x00000007 - ECX
|
|
Bit32u bx_cpuid_t::get_std_cpuid_leaf_7_ecx(Bit32u extra) const
|
|
{
|
|
Bit32u ecx = extra;
|
|
|
|
// [0:0] PREFETCHW1 instruction - not supported
|
|
|
|
// [1:1] AVX512 VBMI instructions
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_VBMI))
|
|
ecx |= BX_CPUID_EXT4_AVX512_VBMI;
|
|
}
|
|
#endif
|
|
|
|
// [2:2] UMIP: Supports user-mode instruction prevention
|
|
if (is_cpu_extension_supported(BX_ISA_UMIP))
|
|
ecx |= BX_CPUID_EXT4_UMIP;
|
|
|
|
// [3:3] PKU: Protection keys for user-mode pages
|
|
// [4:4] OSPKE: OS has set CR4.PKE to enable protection keys
|
|
#if BX_SUPPORT_PKEYS
|
|
if (is_cpu_extension_supported(BX_ISA_PKU)) {
|
|
ecx |= BX_CPUID_EXT4_PKU;
|
|
if (cpu->cr4.get_PKE())
|
|
ecx |= BX_CPUID_EXT4_OSPKE;
|
|
}
|
|
#endif
|
|
|
|
// [5:5] WAITPKG (TPAUSE/UMONITOR/UMWAIT) support - not supported
|
|
|
|
// [6:6] AVX512 VBMI2 instructions support
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_VBMI2))
|
|
ecx |= BX_CPUID_EXT4_AVX512_VBMI2;
|
|
}
|
|
#endif
|
|
|
|
// [7:7] CET_SS: Support CET Shadow Stack
|
|
#if BX_SUPPORT_CET
|
|
if (is_cpu_extension_supported(BX_ISA_CET))
|
|
ecx |= BX_CPUID_EXT4_CET_SS;
|
|
#endif
|
|
|
|
// [8:8] GFNI instructions support
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_GFNI))
|
|
ecx |= BX_CPUID_EXT4_GFNI;
|
|
#endif
|
|
|
|
// [9:9] VAES instructions support
|
|
// [10:10] VPCLMULQDQ instruction support
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_VAES_VPCLMULQDQ))
|
|
ecx |= BX_CPUID_EXT4_VAES | BX_CPUID_EXT4_VPCLMULQDQ;
|
|
#endif
|
|
|
|
// [11:11] AVX512 VNNI instructions support
|
|
// [12:12] AVX512 BITALG instructions support
|
|
// [13:13] reserved
|
|
// [14:14] AVX512 VPOPCNTDQ: AVX512 VPOPCNTD/VPOPCNTQ instructions
|
|
#if BX_SUPPORT_EVEX
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512)) {
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_VNNI))
|
|
ecx |= BX_CPUID_EXT4_AVX512_VNNI;
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_BITALG))
|
|
ecx |= BX_CPUID_EXT4_AVX512_BITALG;
|
|
if (is_cpu_extension_supported(BX_ISA_AVX512_VPOPCNTDQ))
|
|
ecx |= BX_CPUID_EXT4_AVX512_VPOPCNTDQ;
|
|
}
|
|
#endif
|
|
|
|
// [15:15] reserved
|
|
// [16:16] LA57: LA57 and 5-level paging - not supported
|
|
// [17:17] reserved
|
|
// [18:18] reserved
|
|
// [19:19] reserved
|
|
// [20:20] reserved
|
|
// [21:21] reserved
|
|
|
|
// [22:22] RDPID: Read Processor ID support
|
|
if (is_cpu_extension_supported(BX_ISA_RDPID))
|
|
ecx |= BX_CPUID_EXT4_RDPID;
|
|
|
|
// [23:23] Keylocker support - not supported
|
|
// [24:24] reserved
|
|
// [25:25] CLDEMOTE: CLDEMOTE instruction support - not supported
|
|
// [26:26] reserved
|
|
// [27:27] MOVDIRI: MOVDIRI instruction support - not supported
|
|
// [28:28] MOVDIRI64: MOVDIRI64 instruction support - not supported
|
|
// [29:29] ENQCMD: Enqueue Stores support - not supported
|
|
// [30:30] SGX_LC: SGX Launch Configuration - not supported
|
|
|
|
// [31:31] PKS: Protection keys for supervisor-mode pages
|
|
#if BX_SUPPORT_PKEYS
|
|
if (is_cpu_extension_supported(BX_ISA_PKS))
|
|
ecx |= BX_CPUID_EXT4_PKS;
|
|
#endif
|
|
|
|
return ecx;
|
|
}
|
|
|
|
// leaf 0x80000008 - return Intel defaults //
|
|
void bx_cpuid_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const
|
|
{
|
|
// virtual & phys address size in low 2 bytes of EAX.
|
|
// TODO: physical address width should be 32-bit when no PSE-36 is supported
|
|
Bit32u phy_addr_width = BX_PHY_ADDRESS_WIDTH;
|
|
Bit32u lin_addr_width = is_cpu_extension_supported(BX_ISA_LONG_MODE) ? BX_LIN_ADDRESS_WIDTH : 32;
|
|
|
|
leaf->eax = phy_addr_width | (lin_addr_width << 8);
|
|
|
|
// [0:0] CLZERO support
|
|
// [1:1] Instruction Retired Counter MSR available
|
|
// [2:2] FP Error Pointers Restored by XRSTOR
|
|
// [3:3] reserved
|
|
// [4:4] RDPRU support
|
|
// [5:5] reserved
|
|
// [6:6] Memory Bandwidth Enforcement (MBE) support
|
|
// [8:7] reserved
|
|
// [9:9] WBNOINVD support - not supported yet
|
|
leaf->ebx = 0;
|
|
if (is_cpu_extension_supported(BX_ISA_CLZERO))
|
|
leaf->ebx |= 0x1;
|
|
|
|
leaf->ecx = 0; // Reserved, undefined for Intel
|
|
leaf->edx = 0;
|
|
}
|
|
|
|
void bx_cpuid_t::get_cpuid_hidden_level(cpuid_function_t *leaf, const char *magic_string) const
|
|
{
|
|
memcpy(&(leaf->eax), magic_string , 4);
|
|
memcpy(&(leaf->ebx), magic_string + 4, 4);
|
|
memcpy(&(leaf->ecx), magic_string + 8, 4);
|
|
memcpy(&(leaf->edx), magic_string + 12, 4);
|
|
|
|
#ifdef BX_BIG_ENDIAN
|
|
leaf->eax = bx_bswap32(leaf->eax);
|
|
leaf->ebx = bx_bswap32(leaf->ebx);
|
|
leaf->ecx = bx_bswap32(leaf->ecx);
|
|
leaf->edx = bx_bswap32(leaf->edx);
|
|
#endif
|
|
}
|
|
|
|
void bx_cpuid_t::dump_cpuid_leaf(unsigned function, unsigned subfunction) const
|
|
{
|
|
struct cpuid_function_t leaf;
|
|
get_cpuid_leaf(function, subfunction, &leaf);
|
|
BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", function, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx));
|
|
}
|
|
|
|
void bx_cpuid_t::dump_cpuid(unsigned max_std_leaf, unsigned max_ext_leaf) const
|
|
{
|
|
for (unsigned std_leaf=0; std_leaf<=max_std_leaf; std_leaf++) {
|
|
dump_cpuid_leaf(std_leaf);
|
|
}
|
|
|
|
if (max_ext_leaf == 0) return;
|
|
|
|
for (unsigned ext_leaf=0x80000000; ext_leaf<=(0x80000000 + max_ext_leaf); ext_leaf++) {
|
|
dump_cpuid_leaf(ext_leaf);
|
|
}
|
|
}
|
|
|
|
void bx_cpuid_t::warning_messages(unsigned extension) const
|
|
{
|
|
switch(extension) {
|
|
case BX_ISA_3DNOW:
|
|
BX_INFO(("WARNING: 3DNow! is not implemented yet !"));
|
|
break;
|
|
case BX_ISA_RDRAND:
|
|
BX_INFO(("WARNING: RDRAND would not produce true random numbers !"));
|
|
break;
|
|
case BX_ISA_RDSEED:
|
|
BX_INFO(("WARNING: RDSEED would not produce true random numbers !"));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
void bx_cpuid_t::dump_features() const
|
|
{
|
|
BX_INFO(("CPU Features supported:"));
|
|
for (unsigned i=1; i<BX_ISA_EXTENSION_LAST; i++)
|
|
if (is_cpu_extension_supported(i))
|
|
BX_INFO(("\t\t%s", cpu_feature_name[i]));
|
|
}
|