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110 Commits

Author SHA1 Message Date
Stanislav Shwartsman
773f1b7e42 cleanup return value of all instruction handlers 2018-02-16 07:57:32 +00:00
Stanislav Shwartsman
b468316250 re-style old resolve macros after resolve function inlining 2015-05-16 21:06:59 +00:00
Stanislav Shwartsman
9f18573740 Rename BX_CPU_CALL_METHODR to BX_CPU_RESOLVE_ADDR and introduce special cases BX_CPU_RESOLVE_ADDR_64 (for 64-bit mode only) and BX_CPU_RESOLVE_ADDR_32 (for 32-bit mode only) 2015-05-11 19:23:09 +00:00
Stanislav Shwartsman
63c3ed3f70 update (c) and fix instrumentation stub 2015-01-11 20:50:26 +00:00
Stanislav Shwartsman
3b237df41d Added far branch origin to bx_instr_far_branch instrumentation callback by user request 
Updated instrumentation examples
Fixed code duplication
 2015-01-11 20:45:39 +00:00
Stanislav Shwartsman
ea91354b3b code reorg : take laddr calculation out of 64-bit memory handlers. this creates generic linear address memory handlers which now could be used elsewhere 2014-10-20 21:08:29 +00:00
Stanislav Shwartsman
a85a9081b7 use shorter opcode names in the debug prints (skip the BX_IA_ prefix) 2013-12-02 20:06:59 +00:00
Stanislav Shwartsman
d082c6a0f9 implemented avx-512 masked load instructions 2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
c42afb0a2d allow linking of traces cross 4K page boundary 2013-06-23 21:12:03 +00:00
Stanislav Shwartsman
b2b42dd714 small fix for LOAD_SS interrupts inhibit 2013-05-04 19:10:50 +00:00
Stanislav Shwartsman
53d14c01b5 correctly signal bit 12 (nmi unblocking by iret) in vmx interruption info. todo: find how to implement it clean way 2013-03-06 21:11:23 +00:00
Stanislav Shwartsman
1a770dd260 implementation of virtual NMI 2013-03-05 21:12:43 +00:00
Stanislav Shwartsman
ab63b22a68 SVM: implemented missed RSM, LDTR READ/WRITE, TR READ/WRITE and IRET intercepts 2013-02-25 19:36:41 +00:00
Stanislav Shwartsman
8708d05bea rename some VMX controls to match intel docs. added missed VMX consistency check 2013-02-24 20:22:22 +00:00
Stanislav Shwartsman
d5f858d100 transfer VMX NMI window exiting into event vector infrastructure 2012-09-25 10:21:29 +00:00
Stanislav Shwartsman
40ba9c8d7b introducing new interface for handling CPU events based on vector of events and not on many not related variables. this is very initial implementation which takes into new interface only few events, more will code soon 2012-09-25 09:35:38 +00:00
Stanislav Shwartsman
c41cbe6d56 Link traces over taken branch optimization which makes handlers chaining even more efficient. 
I observed 5% speedup in all disk images over 2.6pre1.
The change is safe (passed all regressions) and I will be glad to make it into Bochs 2.6!
 2012-08-21 19:58:41 +00:00
Stanislav Shwartsman
cc694377b9 Standartization of Bochs instruction handlers. 
Bochs instruction emulation handlers won't refer to direct fields of instructions like MODRM.NNN or MODRM.RM anymore.
Use generic source/destination indications like SRC1, SRC2 and DST.
All handlers are modified to support new notation. In addition fetchDecode module was modified to assign sources to instructions properly.

Immediate benefits:
- Removal of several duplicated handlers (FMA3 duplicated with FMA4 is a trivial example)
- Simpler to understand fetch-decode code

Future benefits:
- Integration of disassembler into Bochs CPU module, ability to disasm bx_instruction_c instance (planned)

Huge patch. Almost all source files wre modified.
 2012-08-05 13:52:40 +00:00
Stanislav Shwartsman
d9998269ef added branch_eip into near branch instructiontation callbacks 2012-07-24 15:32:55 +00:00
Stanislav Shwartsman
3ca29cbdf3 stack direct access optimization - 5% emu speedup to all 32-bit guests, for 64-bit guests speedup is less because they have less stack accesses 2012-03-25 11:54:32 +00:00
Stanislav Shwartsman
f6203dae7d instrumentation: added special indication for indirect call/jump 2011-12-18 18:11:56 +00:00
Stanislav Shwartsman
13feb0772a - 10% emulation speedup with handlers chaining optimization implemented. The 
feature is enabled by default when configure with --enable-all-optimizations
    option, to disable handlers chaining speedups configure with
        --disable-handlers-chaining
 2011-08-21 14:31:08 +00:00
Stanislav Shwartsman
002c86660a reword all the CPU code in preparation for future CPU speedup implementation. 
Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
 2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
29e3f6e762 remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache 2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
7d80a6ebe0 Adding Id and Rev property to all files 2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
49c85b07f6 Fixed address size wrap 2010-10-18 22:19:45 +00:00
Stanislav Shwartsman
cffe32dd2c remove unused param from exception() call 2010-03-14 15:51:27 +00:00
Stanislav Shwartsman
9268646239 cleanup and optimization 2010-02-21 06:56:48 +00:00
Stanislav Shwartsman
ef1dadcdd8 cleanup and optimization 2010-02-15 08:42:57 +00:00
Stanislav Shwartsman
bd60e0264c change Copyright to Bochs Project 2009-12-04 16:53:12 +00:00
Stanislav Shwartsman
c9383813f0 don't have to keep both limit and limit_scale 2009-04-05 18:16:29 +00:00
Stanislav Shwartsman
e5be60be64 Fixed lazy flags bug I added in one of my prev merges 
ICACHE code reorganization
 2009-03-22 21:12:35 +00:00
Stanislav Shwartsman
9e723a044f - Added configure option to enable/disable A20 pin support. Disabling the 
A20 pin support slightly speeds up the emulation.

  - small code cleanup
 2009-03-10 16:28:01 +00:00
Stanislav Shwartsman
592484408f Initial NMI virtualization for VMX, clean out CPU pins set/clear code 2009-02-03 19:17:15 +00:00
Stanislav Shwartsman
9929e6ed78 - updated FSF address 2009-01-16 18:18:59 +00:00
Stanislav Shwartsman
098308dd9f some variable renames + comp warn fix 2008-12-01 19:06:14 +00:00
Stanislav Shwartsman
c1306f7d75 small non-significant speedups 2008-09-06 21:10:40 +00:00
Stanislav Shwartsman
f275eb3e86 - CALL instructions should push old EIP to stack before checking new EIP for CS.limits 2008-08-16 15:32:44 +00:00
Stanislav Shwartsman
1da5943f1a More use of LOAD_Ex method 2008-08-10 19:34:28 +00:00
Stanislav Shwartsman
5dd02b26e3 Make even more efficient RmAddr calculation - good optimizing compiler could make more efficient code than it was before 2008-08-08 09:22:49 +00:00
Stanislav Shwartsman
b65816a92d Fixed problem in my morning checkin + some more changes 2008-06-23 15:58:22 +00:00
Stanislav Shwartsman
678ac970aa Reorganize ctrl_xfer8.cc code, allows to inline branch32 method 2008-06-22 03:45:55 +00:00
Stanislav Shwartsman
bef3450baa Fixes to 64-bit mode 2008-05-11 20:46:11 +00:00
Stanislav Shwartsman
ec1ff39a5f Splitted memory access methods for 32 and 64-bit code. 
The 64-bit code got >10% speedup, the 32-bit code also got about 2% because laddr cacluation optimization
 2008-05-10 18:10:53 +00:00
Stanislav Shwartsman
09c875b11c Fixed dbg comment 2008-05-08 21:04:03 +00:00
Stanislav Shwartsman
3dc0438c43 Implemented CALL_Far64 and JMP_Far64 according to Intel docs 2008-04-13 20:57:49 +00:00
Stanislav Shwartsman
167c7075fb Use fastcall gcc attribute for all cpu execution functions - this pure "compiler helper" optimization brings additional 2% speedup to Bochs code 2008-03-22 21:29:41 +00:00
Stanislav Shwartsman
a2897933a3 white space cleanup 2008-02-02 21:46:54 +00:00
Stanislav Shwartsman
37fbb82baa Cleanups. Move bxInstruction_c definition to separate file instr.h 2008-01-29 17:13:10 +00:00
Stanislav Shwartsman
c6fd4ebf94 Split CALL_Ev and JMP_Ev methods 2008-01-12 16:40:38 +00:00