Stanislav Shwartsman
58470763fa
implement few more avx-512 opcodes
2013-12-31 23:51:25 +00:00
Stanislav Shwartsman
350e3544ae
fixed #UD condition for multi-byte prefix opcodes VEX/EVEX/XOP
2013-12-28 12:57:21 +00:00
Stanislav Shwartsman
15756a31cd
implemented EVEX MOVD/MOVQ opcodes, fixes in softfloat
2013-12-13 12:05:47 +00:00
Stanislav Shwartsman
9c179bade8
fixed evex.b validation condition
2013-12-10 21:48:17 +00:00
Stanislav Shwartsman
258a60f3fa
Implemented AVX512 EXPAND/COMPRESS instructions
...
Fixed memory access size for AVX shift instructions with shift count in memory
Do not allow to encode with EVEX.b instructions which do not support implicit broadcast
softfloat: prepare float32/64 to uint32 conversion functions
2013-12-10 21:09:46 +00:00
Stanislav Shwartsman
d20c81417c
Implemented VSHUFF32x4/64x2, VSHUFI32x4/64x2 AVX512 instructions
...
Implemented AVX512 blend instructions
Do not allow setting of EVEX.b in reg form when no floating point exceptions could be generated by instruction
2013-12-09 19:09:37 +00:00
Stanislav Shwartsman
1e474ede51
fixed corrupted fetchdecode from svn rev12001
2013-12-07 20:30:27 +00:00
Stanislav Shwartsman
8c3d0aed7a
added #UD condition for wrong EVEX.LL setting
2013-12-05 20:40:53 +00:00
Stanislav Shwartsman
cfc8a0ad38
get rid of BX_MEM_NO_VVV decoding form (by splitting just two opcode groups using Split11B)
2013-12-04 20:15:22 +00:00
Stanislav Shwartsman
0683b00535
implemented more avx-512 opcodes
2013-12-02 19:16:48 +00:00
Stanislav Shwartsman
7db6c647b0
fixed memory access decoding in presence of evex prefix
2013-11-30 18:51:27 +00:00
Stanislav Shwartsman
d082c6a0f9
implemented avx-512 masked load instructions
2013-11-30 18:37:25 +00:00
Stanislav Shwartsman
f76c85dca9
fixed 512-bit VL encoding in EVEX
2013-11-29 21:05:29 +00:00
Stanislav Shwartsman
11f082af82
Implemented VMOVDQU32/VMOVDQA32/VMOVDQU64/VMOVDQA64 AVX512 instructions
...
Implemented VCOMISS/VCOMISD/VUCOMISS/VUCOMISD AVX512 instructions
Fix vector length values for AVX-512 (512-bit vector should have length 4)
support mis-alignment #GP exception for VMOVAPS/PD/DQA32/DQ64 AVX512 instructions
move AVX512 load/store and register move operations into dedicated file avx512_move.cc
2013-11-29 20:22:31 +00:00
Stanislav Shwartsman
1a735e9fdf
bugfix for decoding segment prefix with EVEX
2013-11-28 21:28:50 +00:00
Stanislav Shwartsman
7f8429c643
fix code duplication in fetchdecode modules
2013-11-20 16:00:24 +00:00
Stanislav Shwartsman
3be7e5884b
added lock prefix used info into bx_Instriction_c and use it in disasm
2013-11-08 21:43:21 +00:00
Stanislav Shwartsman
39f2f172b5
fixed PAUSE/NOP decoding bug in prev commit
2013-10-16 05:46:57 +00:00
Stanislav Shwartsman
8bcc8cf073
split PREFETCH opcode to Group16 for better disasm of bxInstruction_c
2013-10-15 21:21:28 +00:00
Stanislav Shwartsman
940c2a1c8e
fixes for disasm
2013-10-15 17:19:18 +00:00
Stanislav Shwartsman
9fb7384e6b
finish sse tables cleanup in disasm and fetchdecode
2013-10-11 20:09:51 +00:00
Stanislav Shwartsman
34025e469f
resolve aliases after actually decoding base instr
2013-10-11 05:54:18 +00:00
Stanislav Shwartsman
46e36b463b
size-optimization for SSE opcode tables
2013-10-10 20:21:15 +00:00
Stanislav Shwartsman
0b2e533a55
more avx512 instructions done
2013-10-09 19:45:36 +00:00
Stanislav Shwartsman
09254eb474
avx512 implementation fixes and next steps
2013-10-08 18:31:18 +00:00
Stanislav Shwartsman
5724013e7d
updates to AVX512 decoding and CPUID
2013-10-07 20:39:34 +00:00
Stanislav Shwartsman
cb0eee9456
disasm fixes
2013-10-07 19:02:53 +00:00
Stanislav Shwartsman
059769e2a6
disasm bug fixes
2013-10-06 20:42:13 +00:00
Stanislav Shwartsman
d4bfbffdbb
disasm fixes
2013-10-05 08:34:09 +00:00
Stanislav Shwartsman
ba1249ed15
disasm fixes
2013-10-04 17:26:56 +00:00
Stanislav Shwartsman
85b0402668
fixes for disasm
2013-10-02 19:23:34 +00:00
Stanislav Shwartsman
fd383435f0
- Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon).
...
The code already knows to disasm most of the opcodes with their operands.
- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance
- Minimize amount of opcode forms in ia_opcodes.h again.
For example Udq means the same as Wdq but with no memory form.
2013-09-30 19:01:42 +00:00
Stanislav Shwartsman
fa06b26c88
Make possible to deliver instruction name for disasm directly from bx_ia_opcode_name (some opcodes were renamed).
...
Fixed bug in stack optimization in 64-bit mode (should result in some speedup)
ia_opcode.h - eliminate some OP_M cases when they actually meant "value of specific type in the memory"
example: "MOVBE Md, Gd" actually means "MOVBE Ed, Gd"which just not have reg/reg form.
2013-09-26 18:54:32 +00:00
Stanislav Shwartsman
839b841c38
added register type to register source information in decoder
2013-09-24 09:50:25 +00:00
Stanislav Shwartsman
ff79cbd596
Infrstructure change to support disasm of BxInstruction_c directly (without calling disasm)
...
The end goal will be also merging of disasm and cpu decoder to one module and remove the disasm.
Two bug fixes on the way:
TBM: fixed 64-bit TBM instructions with memory access (did 32-bit load instead of 64-bit)
BMI2: fixed operands order for PEXT/PDEP instructions
AVX2: fixed gather instruction decoding bug from decoder alias commit
2013-09-24 05:21:00 +00:00
Stanislav Shwartsman
404b8b1475
move end of trace indication to separate 'flags' field of bx_ia_opcode. this saves a lot of code duplication and simplifies the decode tables. also on the way found missing SVM opcodes that missed 'end of trace' mark
2013-09-21 18:58:01 +00:00
Stanislav Shwartsman
2526282ed9
small additions for avx512
2013-09-20 18:27:33 +00:00
Stanislav Shwartsman
8b3a0acde9
implement first EVEX instructions - VADDPS/PD/SS/SD
2013-09-19 18:31:30 +00:00
Stanislav Shwartsman
8e71a86542
seve vex prefix value to the indication of vex prefix used
2013-09-18 18:01:48 +00:00
Stanislav Shwartsman
aa25c1db6a
name convention change - search and replace
2013-09-17 17:34:20 +00:00
Stanislav Shwartsman
0cb0acc30f
added evex decode tables - next step to populate them :)
2013-09-15 20:48:39 +00:00
Stanislav Shwartsman
7297323c69
First step of AVX512 support implementation (simplest)
...
decode and implement KMASK manipulation instructions
disasm: coming soon
2013-09-08 19:19:16 +00:00
Stanislav Shwartsman
a6b85d9443
compress xop tables for vex.l - smaller binary size
2013-09-06 18:56:46 +00:00
Stanislav Shwartsman
2c9cf33b2f
update (c) for few files
2013-09-05 18:37:10 +00:00
Stanislav Shwartsman
69f947cef2
fixes and small optimizations for avx and xop decoding
2013-09-05 18:29:50 +00:00
Stanislav Shwartsman
f36364bc65
it doesn't matter if it was vex or xop ...
2013-09-05 17:52:47 +00:00
Stanislav Shwartsman
2f957bf142
re-arrange AVX/XOP table to avoid redundant multiplication in decode. TODO: compress the tables 2x using aliases
2013-09-04 18:36:01 +00:00
Stanislav Shwartsman
81affbe328
fixed incorrect lock prefix detection
2013-08-30 20:08:04 +00:00
Stanislav Shwartsman
59c65151f5
various fixes
2013-08-29 19:43:15 +00:00
Stanislav Shwartsman
7e2ab5ca81
decode simplification for AMD XOP prefix
2013-08-28 19:56:19 +00:00
