Stanislav Shwartsman
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46366b5064
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Speedup simulation by eliminating CPL==3 check from read/write_virtual* functions
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2007-12-16 21:03:46 +00:00 |
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Stanislav Shwartsman
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de5838ce80
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cleanups and fixes for Immediate_IbIb of SSE4A
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2007-12-16 20:47:10 +00:00 |
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Stanislav Shwartsman
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8b5eaa5820
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Make functions inline
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2007-12-16 20:37:59 +00:00 |
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Stanislav Shwartsman
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1e843cb462
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Decode SSE4A
Rework immediate bytes decoding to make it faster
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2007-12-15 17:42:24 +00:00 |
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Stanislav Shwartsman
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3a6d714398
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Split for JMP_Ew/Ed opcodes from Grp5
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2007-12-14 23:15:52 +00:00 |
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Stanislav Shwartsman
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fd73390ca5
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Split 64-bit CMOVcc opcode
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2007-12-14 22:41:43 +00:00 |
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Stanislav Shwartsman
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903f6dea35
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Split setCC functions - makes code faster and simpler
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2007-12-14 21:29:36 +00:00 |
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Stanislav Shwartsman
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d9a59c7a1f
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Added ability to merge traces cross JCC branch instructions
Makes traces longer -> emulation faster in average
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2007-12-14 20:41:09 +00:00 |
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Stanislav Shwartsman
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db69a25c36
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Trace cache instrumentation methods
Next step will be tracing cross non-taken branches
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2007-12-14 11:27:44 +00:00 |
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Stanislav Shwartsman
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48d815427c
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According to AMD docs INVLD/WBINVLD instructions not required to flush TLBs
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2007-12-14 10:15:12 +00:00 |
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Stanislav Shwartsman
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c3e5c71000
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post exceptions and print BX_ERROR messages in tasking.cc
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2007-12-13 23:17:50 +00:00 |
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Stanislav Shwartsman
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85d10e4f72
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Added MWAIT callback
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2007-12-13 21:41:32 +00:00 |
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Stanislav Shwartsman
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f145f4c847
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Unify BX_INSTR_MEM_READ and BX_INSTR_MEM_WRITE callbacks to single callback BX_INSTR_MEM_ACCESS
Enable the callback with guest-to-host TLB enabled
Update instrumentation docs
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2007-12-13 21:30:05 +00:00 |
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Stanislav Shwartsman
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05c7a1e61b
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Fixed problem with trace cache enabled
String instructions might confise trace cache by finishing instruction execution method without actually completing an instruction (and advancing eip)
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2007-12-13 18:42:31 +00:00 |
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Stanislav Shwartsman
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05a5923971
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Merged Bochs instrumentation patch by Lluis Vilanova
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2007-12-13 17:16:21 +00:00 |
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Stanislav Shwartsman
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da19b9447a
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All Jq instructions in 64-bit mode have fixed 64-bit osize
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2007-12-10 23:04:18 +00:00 |
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Stanislav Shwartsman
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e15f7445f8
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Faster memory access for 4G limit cases
A bit slower for <4G but usually it is 4G
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2007-12-10 19:08:13 +00:00 |
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Stanislav Shwartsman
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adda3befd3
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Trace cache optimization merged
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2007-12-09 18:36:05 +00:00 |
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Stanislav Shwartsman
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ee465a7714
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misaligned SSE support works only for loads
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2007-12-09 17:40:23 +00:00 |
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Stanislav Shwartsman
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29267577f0
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Fixed HLT problem in SMP binary which runs with single processor only
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2007-12-08 09:26:13 +00:00 |
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Stanislav Shwartsman
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976af56f6d
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Split bit.cc to 4 files - new files bit16/32/64.cc
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2007-12-07 10:59:18 +00:00 |
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Stanislav Shwartsman
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4c16dd71a8
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Fixed compilation error in SMP mode
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2007-12-07 09:38:42 +00:00 |
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Stanislav Shwartsman
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6fcc7d34ab
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Next step in lazy flags optimization by Darek MihockA -
get rid of shifts from lazy flags code
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2007-12-06 20:39:11 +00:00 |
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Stanislav Shwartsman
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d739cca282
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small cleanup
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2007-12-06 18:35:33 +00:00 |
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Stanislav Shwartsman
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d54d537f81
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One more step for lazy flags optimization
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2007-12-06 16:57:59 +00:00 |
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Stanislav Shwartsman
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a835e3f8ff
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get_FLAG_Lazy not always returns 0/1
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2007-12-05 06:27:01 +00:00 |
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Stanislav Shwartsman
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295a36ef58
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2nd step of lazy flags optimization
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2007-12-05 06:17:09 +00:00 |
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Stanislav Shwartsman
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88899cf617
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Changes for lazy flags handling -> 1st stap in transition to new lazy flags handling by Darek Mihocka (www.emulators.com)
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2007-12-04 19:27:23 +00:00 |
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Stanislav Shwartsman
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40fc0a3e42
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Reduce ICACHE back to 32K entries - reduce ICACHE size from 4M to 2M
Not everybody already have C2D CPU with 4M L2 cache on die ...
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2007-12-04 17:34:20 +00:00 |
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Stanislav Shwartsman
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91e0db63c4
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no need to invalidate prefetch queue for RDMSR/WRMSR
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2007-12-03 21:43:14 +00:00 |
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Stanislav Shwartsman
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c58e95f611
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Make hw breakpoint match check a function - normally it should be called from read/write_virtual as well
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2007-12-03 20:49:24 +00:00 |
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Stanislav Shwartsman
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dbfa7a51e9
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Do not affect CPU state if any exception occured - in this case do not write to MEM and flags
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2007-12-03 20:48:02 +00:00 |
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Stanislav Shwartsman
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1bcf42baec
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oops, fixed incorrect checkin
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2007-12-01 16:59:36 +00:00 |
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Stanislav Shwartsman
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7ca78b88e9
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configure/compile changes + small optimizations
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2007-12-01 16:45:17 +00:00 |
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Stanislav Shwartsman
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d1e71ec4a7
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deliver smi should be available even if apic is OFF
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2007-11-30 17:59:10 +00:00 |
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Stanislav Shwartsman
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a0147fe055
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Fixed bug prevented to boot Win98
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2007-11-30 08:49:12 +00:00 |
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Stanislav Shwartsman
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39b2680110
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Fixed compilation error when x86-64 emualtion disabled
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2007-11-29 22:22:24 +00:00 |
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Stanislav Shwartsman
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aa00d33640
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BITSCAN lazy flags evaluation optimization
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2007-11-29 21:52:16 +00:00 |
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Stanislav Shwartsman
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1a55835155
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Optimize lazy flags for MUL/IMUL
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2007-11-29 21:45:10 +00:00 |
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Stanislav Shwartsman
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8cfd17202a
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some simple SSE code optimizations
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2007-11-27 22:12:45 +00:00 |
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Stanislav Shwartsman
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91add6a05a
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cleanup
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2007-11-26 17:45:48 +00:00 |
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Stanislav Shwartsman
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35c3791bb7
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Correctly implement EFER.FFXSR feature
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2007-11-25 20:52:40 +00:00 |
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Stanislav Shwartsman
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c51888f43f
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Split last BxLockable opcodes -> this allows to eliminate mod==0xc0 check from fetchdecode of every instruction
reduce ACPU.CC dependencies - now that file doesn't depend of CPU
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2007-11-25 20:22:10 +00:00 |
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Stanislav Shwartsman
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42d06b2d2b
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make some functions RSP safe so it is not needed to save/restore RSP for the anymore
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2007-11-24 15:27:55 +00:00 |
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Stanislav Shwartsman
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e51184c8cf
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Eliminate saving of RSP from heart of cpu_loop
Now save RSP only where it is really required
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2007-11-24 14:22:34 +00:00 |
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Stanislav Shwartsman
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d0052dcd3e
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Removed unused setFlags code
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2007-11-23 22:49:54 +00:00 |
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Stanislav Shwartsman
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3daa468c02
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Fixed comments in bit.cc
Revert back lock prefix changes in fetchdecode - not all lockable instructions are splitted yet ;(
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2007-11-23 16:37:06 +00:00 |
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Stanislav Shwartsman
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af9a14ff3b
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cleanups
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2007-11-22 21:52:55 +00:00 |
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Stanislav Shwartsman
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1dbe51a2fb
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Split ENTER_IwBw function according to os32. Fixed ENTER/LEAVE in 64-bit mode
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2007-11-22 17:33:06 +00:00 |
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Stanislav Shwartsman
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e0ee0eaaaf
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Diplicate ICACHE size - now index to ICACHE is exactly 16 bit so ICACHE hash function could be computed more efficiently
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2007-11-22 17:32:00 +00:00 |
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