register for proper operation. Add a prototype field in the pciide_channel
for this register and use it as necessary when writing the IDEDMA_CMD
register.
D-Link DGE-530T
Linksys EG1032v2
Linksys EG1064v2
The Linux driver treats all of these the same. Tested with a DGE-530T;
it works, though performance on at least one of my systems is atrocious.
Fix setting of ethernet capabilities into interface capabilites word in
attach routine.
Manual page: note that jumbo support doesn't work and checksum support
doesn't exist.
* add constants to enums
* HAL update: stops panics, fixes ad hoc-mode beacons, some API
changes
* get and use mac/phy/rf front-end revision codes
* add a custom ath(4) ic_node_getrssi callback which does RSSI
averaging
* do not immediately scan, but re-associate after missing beacons.
* bug fix: don't if_init after detach.
* HAL diagnostics ioctl, SIOCGATHDIAG
* send DS parameters element in beacons
* const-ify some pointers
* consolidate rx-filter settings into ath_calcrxfilter
* abstract FreeBSD `ticks', NetBSD `hardclock_ticks' with ATH_TICKS()
* misc. other changes
Fix some non-initialized variables
close the output files when done
Redo the printing for RCS strings so they don't expand in the awk script too
Do proper tests for variables existance before accessing
Verified output from all scripts is identical to original versions
including chips that matched only the asic-revision fallback table.
When dong DMA setup for 5703 and 5704, use the new BGE_ASICREV() macro
to extract the ASIC revision.
True IDE mode. Hinted at by Charles Hannum a while back. This lets
my PCI-Cardbus adapter read SanDisk CF cards much more reliably.
Also bring in a few defines from FreeBSD for some more TI registers and such.
APs to run at "full speed" where before they ran at just 1 or 2Mb/s.
The AP will adapt the data rate for each client based on packet
losses and the received signal strength.
I have also enabled rate adaptation for STA mode and for IBSS mode,
but the hardware gives us less control over the data rate in those
modes.
o Add support for the recent SiS96x chipsets that have a new revision.
That includes a new bit of code to access the EEPROM, since it is
shared with the ieee1394 controller on those chipsets.
Mostly taken from FreeBSD (rev. 1.62 and 1.64 of sys/pci/if_sip.c). I
tried to make the code look less ugly, but couldn't invent documentation.
Fix PR #23481. Thanks to Stephane ENGEL <sengel AT melshake DOT com> for
the report and the cheerful testing.
assert IDEDMA_CTL_INTR for non-DMA commands.
It would be nice to have a way to know if the interrupt was for us or not at
this point, but for now let wdcintr() deal with it.
Problem reported and patch tested by Martti Kuparinen.
in a different fashion. Individually, they have the same functionality,
but their layout is different. An example of such a chipset is
the Promise 203xx.
To be able to deal with this, transform the cmd and dma bus_space handles
into an array of handles, each seperately created with bus_space_subregion.
The code generated by using the extra indirection shouldn't change much,
since the extra indirection is negated by having the offset calculation
already done in bus_space_subregion. E.g.
bus_space_write_4(tag, handle, offset, value)
becomes
bus_space_write_4(tag, handles[offset], 0, value)
Reviewed by Manuel Bouyer. Tested on wdc_isa, wdc_pcmcia, viaide, piixide (i386)
and on cmdide (sparc64).
different meanings for read and write.
This fixes 48kHz playback to SPDIF.
- Fix the problem where the SPDIF output voltage setting (0.5V, 5V)
was swapped. The default value is changed from 0.5V to 5V, which
correctly selects 5V (so the default physical behavior is unchanged).
Should fix PRs kern/16047 and kern/16817
(but not tested since I don't have other SPDIF hardware to test with).
Approved by tshiozak.
- tweak some attach messages
- establish interrupt after all dma resouces are successfully allocated
- wrap an assertion with #ifdef DIAGNOSTIC
- assume NCRCFG2_FE bit is always enabled
- call bus_dmamap_sync for mdldmap at POSTWRITE for consistency
- pass proper dmamapsize for mdldmap
Not tested on 795[56], but compiles and matches FreeBSD-tested diffs.
Suggested by Sam Leffler <sam@errno.com>, as imported into FreeBSD by Sam.
Submitted to FreeBSD by Rajesh Vaidyanath <RVaidyanath@hifn.com>.
This reloads the entire EEPROM, not just the MAC address, which can
cause problems for the host PCI bus under certain circumstances. The
chip already loads the EEPROM at powerup/reset anyway.
XXX: This probably applies to the other Rhine variants too, but I don't
have a data sheet to confirm this behaviour.
copyin() or copyout().
uvm_useracc() tells us whether the mapping permissions allow access to
the desired part of an address space, and many callers assume that
this is the same as knowing whether an attempt to access that part of
the address space will succeed. however, access to user space can
fail for reasons other than insufficient permission, most notably that
paging in any non-resident data can fail due to i/o errors. most of
the callers of uvm_useracc() make the above incorrect assumption. the
rest are all misguided optimizations, which optimize for the case
where an operation will fail. we'd rather optimize for operations
succeeding, in which case we should just attempt the access and handle
failures due to insufficient permissions the same way we handle i/o
errors. since there appear to be no good uses of uvm_useracc(), we'll
just remove it.
* erratum: disable the nocrc RX bit, as it may cause problems on the 570{1-4}.
adjust the length of the incoming packet accordingly to trim it.
* the 5704 has a smaller MBUF_POOL, so set a smaller value
Local change:
* Pass the autoneg force flag to mii_attach. Some PHYs need to be kicked
out of their falsely autoneged 10baseT state with this.
initialized. Update the txp(4) to compensate.
- Statically initialize the TCP timer callout handles in the tcpcb
template. We still use callout_setfunc(), but that call is now much
less expensive. Add a comment that the compiler is likely to unroll
the loop (so don't sweat that it's there).
* don't set the NOCRC bit in the mode control register, it can cause
problems on some chips (from the broadcom errata via FreeBSD)
* implement a fallback quirktable that is searched only using the
major asic revision, so that the driver has a shot at supporting
newer versions properly without modification
* rename asicrev -> chipid, like the FreeBSD driver
According to the ICH datasheets, the flag is unchanged unless resetting
the codec.
The flag is useless after enabling bus mastering. This behavior is common
to all ICH chips. The quirk handling code is removed.
chips. Add the i82541 and i82547 product IDs to the table, #if 0'd
out, for now (there are still more changes to come for these new chips
to work properly).
max memory read byte count in the command register is <= the max designed
memory read byte count in the status register. If not, reset it to the
status register's value. This is necessary because some BIOSes configure
the wrong value, and the wrong value confused some versions of the PCI-X
capable chips.
command register bits offset and shifted appropriatly (PCI-X command
makes up the upper 16 bits of the register that holds the PCI-X cap ID
and next-cap-pointer).
- Define shift counts for max memory read byte count in the command
and status registers.
normal operation, it is required to implement a bug work-around on
some chips.
- When issuing a reset on the i82544, i82540, i82545, i82546,
and i82541, use I/O space, if available, to work around a problem
with the memory write cycle (problem only occurs when issuing
a reset).
only single segment.
- No need to set VR_CMD_TX_ON in vr_start().
- Initialize BCR0 and BCR1 registers.
- Change RX DMA threshold 128bytes.
Mostly from FreeBSD via OpenBSD.
We can only attach an ath(4) on architectures where we have a HAL
(which is only x86, for now) so I list the files belonging to the
PCI front-end separately from the other PCI files.
http://mail-index.netbsd.org/tech-kern/2003/09/25/0007.html
We now have:
acardide* at pci? dev ? function ? # Acard IDE controllers
aceride* at pci? dev ? function ? # Acer Lab IDE controllers
cmdide* at pci? dev ? function ? # CMD tech IDE controllers
cypide* at pci? dev ? function ? # Cypress IDE controllers
hptide* at pci? dev ? function ? # Triones/HighPoint IDE controllers
optiide* at pci? dev ? function ? # Opti IDE controllers
piixide* at pci? dev ? function ? # Intel IDE controllers
pdcide* at pci? dev ? function ? # Promise IDE controllers
siside* at pci? dev ? function ? # SiS IDE controllers
slide* at pci? dev ? function ? # Symphony Labs IDE controllers
viaide* at pci? dev ? function ? # VIA/AMD/Nvidia IDE controllers
pciide* at pci? dev ? function ? flags 0x0000 # GENERIC pciide driver
serverworks driver not commited yet; there are still copyright issues about
it.
http://mail-index.netbsd.org/tech-kern/2003/09/25/0006.html
This adds a device (atabus) between IDE controllers and wd or atapibus, to
have each ATA channel show up in the device tree. Later there will be atabus
devices in /dev, so that we can do IOCTL on them.
Each atabus has its own kernel thread, to handle operations that needs polling,
e.g. reset and others.
Device probing on each bus it defered to the atabus thread creation.
This allows to do the reset and basic device probes in parallel, which reduce
boot time on systems with several pciide controllers.
removing assumptions that there are only two B channels and by
adding support for a varying number of channels.
Due to this, rename previously used isdn identified "bri" to "isdnif",
which better describes the current situation.
* auich_calibrate() assumes that the AC97 part is in its reset state. To
ensure this, call audio_attach_mi() after auich_calibrate().
* Explicitly support 12000Hz and 24000Hz. (Why is there a discrete list at
all?)
* Fix an obvious recording bug -- we were acking the wrong interrupt.
* Ensure that we don't get an interrupt during the AC97 speed probe by clearing
the "interrupt on completion" bit in the DMA setup.
interface controllers (of varying intelligence levels).
Contributed by Wasabi Systems, Inc. Primarily written by Steve Woodford,
with some modification by me.
to pci_attach_args. The latter is allocated on the stack during auto-
configuration and so will not be valid after that time.
It's amazing how the old code worked for so long. I guess pci_attach_args
is allocated deep in pid#0's kernel stack on most platforms.
- if_bcereg.h should only have register definitions, so declarations
of softc structure etc. should be in if_bce.c.
- The types of DMA descriptors should be u_int32_t, not unsigned long.
- netinet headers are not required here.
- Values passed via bce_tx_ring should also be byte-swapped.
- byte-swapping is not needed for bus_space access.
from me:
- KNF
- mark all magic numbers with /* MAGIC */ so they can be identified at
some point. there are 33 in total though many appear to be the same
value, or related (eg, the 6 emac points.)
leaves these issues:
- RX pre-packet headers need to be byte-swapped or not?
- PAGE_SIZE bytes are allocated for both TX and RX DMA ring descriptors,
but they should be 1024 (== sizeof(struct bce_dma_slot) * N[TR]XDESC).
- the mcast filter.
The driver backend is capable of supporting also ISA cards (no DMA)
and primary rate (PRI) cards in addition to the basic rate ones,
but I don't any to test on right now, so we don't support those
currently.
This code was originally written by Juha-Matti Liukkonen <jml@cubical.fi>
of Cubical Solutions Ltd. for FreeBSD, and was ported to NetBSD by
myself for the same company.
CCB is returned to the caller.
- Make code paths that can use twe_ccb_alloc_wait() use it, and assert
that a CCB is always returned from that function.
- Assert that a CCB is always returned when allocating the reserved CCB
for an AEN fetch.
reserved CCB. This means that all remaining callers of twe_param_get*()
are called from a valid thread context, and thus have no need to use a
reserved CCB. This will allow for further cleanup in a future commit.
1) Don't wait for DRQ on an IDENTIFY command -- if it's not set when we see
BSY clear, abort the command and ignore the drive. (Do this by testing
for DRQ in the read/write cases in __wdccommand_intr().)
2) Don't wait for DRQ to deassert when we finish an IDENTIFY (or any other
non-block command that reads data) -- we don't do this for block I/O, and
empirically it doesn't clear on my CF cards at all, causing a pointless 1s
delay.
3) Add comments to some of the delay()s, and add missing ones in wdcreset()
and the WDCC_RECAL in the so-called "pre-ATA" probe.
4) Slightly simplify the reset sequence -- we were doing an extra I/O.
5) Modify the register writability test to make sure that registers are not
overlapped -- this can happen in some weird cases with a missing device 1.
6) Check the error register value after the reset -- if it's not 01h or 81h,
as appropriate (see ATA spec), punt.
Tested with a number of ATA-only, ATAPI-only, mixed ATA-ATAPI, CF, and IDE
disk configurations.
Also remove the SINGLE_DRIVE nonsense again.
- Make AENs use the generic code table stuff.
- Add a few more AEN codes (from FreeBSD).
- Correct the context of a few AEN codes (some were listed as
"unit context" when they're really "port context").
- Add a queue of AENs that management tools in userspace can poll
(from FreeBSD).
