No need to check the codec ready flag in read_codec() and write_codec().
According to the ICH datasheets, the flag is unchanged unless resetting the codec. The flag is useless after enabling bus mastering. This behavior is common to all ICH chips. The quirk handling code is removed.
This commit is contained in:
kent
parent
e93422fa5f
commit
27d4af4355
@ -1,4 +1,4 @@
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/* $NetBSD: auich.c,v 1.45 2003/10/22 15:57:33 manu Exp $ */
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/* $NetBSD: auich.c,v 1.46 2003/10/23 05:25:29 kent Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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@ -115,7 +115,7 @@
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.45 2003/10/22 15:57:33 manu Exp $");
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__KERNEL_RCSID(0, "$NetBSD: auich.c,v 1.46 2003/10/23 05:25:29 kent Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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@ -207,7 +207,6 @@ struct auich_softc {
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pt;
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#endif
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int sc_ignore_codecready;
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/* SiS 7012 hack */
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int sc_sample_size;
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int sc_sts_reg;
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@ -327,33 +326,25 @@ static const struct auich_devtype {
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int product;
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const char *name;
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const char *shortname;
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int quirks;
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#define QUIRK_IGNORE_CODEC_READY 0x01
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#define QUIRK_IGNORE_CODEC_READY_MAYBE 0x02
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} auich_devices[] = {
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AA_ACA,
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"i82801AA (ICH) AC-97 Audio", "ICH" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801AB_ACA,
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"i82801AB (ICH0) AC-97 Audio", "ICH0",
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QUIRK_IGNORE_CODEC_READY_MAYBE },
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"i82801AB (ICH0) AC-97 Audio", "ICH0" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_ACA,
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"i82801BA (ICH2) AC-97 Audio", "ICH2",
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QUIRK_IGNORE_CODEC_READY_MAYBE },
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"i82801BA (ICH2) AC-97 Audio", "ICH2" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82440MX_ACA,
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"i82440MX AC-97 Audio", "440MX" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801CA_AC,
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"i82801CA (ICH3) AC-97 Audio", "ICH3" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801DB_AC,
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"i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4",
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QUIRK_IGNORE_CODEC_READY_MAYBE },
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"i82801DB/DBM (ICH4/ICH4M) AC-97 Audio", "ICH4" },
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{ PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_AC,
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"i82801EB (ICH5) AC-97 Audio", "ICH5",
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QUIRK_IGNORE_CODEC_READY },
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"i82801EB (ICH5) AC-97 Audio", "ICH5" },
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{ PCI_VENDOR_SIS, PCI_PRODUCT_SIS_7012_AC,
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"SiS 7012 AC-97 Audio", "SiS7012" },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_MCP_AC,
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"nForce MCP AC-97 Audio", "nForce-MCP",
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QUIRK_IGNORE_CODEC_READY },
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"nForce MCP AC-97 Audio", "nForce-MCP" },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_MCPT_AC,
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"nForce2 MCP-T AC-97 Audio", "nForce-MCP-T" },
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{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_MCPT_AC,
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@ -401,7 +392,6 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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pcireg_t csr;
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const char *intrstr;
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const struct auich_devtype *d;
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u_int32_t status;
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aprint_naive(": Audio controller\n");
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@ -467,10 +457,6 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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sc->sc_sample_size = 2;
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}
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if (d->quirks & QUIRK_IGNORE_CODEC_READY) {
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sc->sc_ignore_codecready = TRUE;
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}
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/* Workaround for a 440MX B-stepping erratum */
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sc->sc_dmamap_flags = BUS_DMA_COHERENT;
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if (d->vendor == PCI_VENDOR_INTEL
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@ -486,6 +472,7 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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DPRINTF(ICH_DEBUG_DMA, ("auich_attach: lists %p %p %p\n",
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sc->dmalist_pcmo, sc->dmalist_pcmi, sc->dmalist_mici));
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#if 0
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/* Reset codec and AC'97 */
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auich_reset_codec(sc);
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status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS);
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@ -499,6 +486,7 @@ auich_attach(struct device *parent, struct device *self, void *aux)
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return;
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}
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}
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#endif
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sc->host_if.arg = sc;
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sc->host_if.attach = auich_attach_codec;
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@ -535,12 +523,6 @@ auich_read_codec(void *v, u_int8_t reg, u_int16_t *val)
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int i;
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uint32_t status;
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status = bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS);
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if (!sc->sc_ignore_codecready && !(status & ICH_PCR)) {
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printf("auich_read_codec: codec is not ready (0x%x)\n", status);
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*val = 0xffff;
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return -1;
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}
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/* wait for an access semaphore */
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for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- &&
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bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1;
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@ -571,11 +553,6 @@ auich_write_codec(void *v, u_int8_t reg, u_int16_t val)
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int i;
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DPRINTF(ICH_DEBUG_CODECIO, ("auich_write_codec(%x, %x)\n", reg, val));
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if (!sc->sc_ignore_codecready
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&& !(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR)) {
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printf("auich_write_codec: codec is not ready.");
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return -1;
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}
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/* wait for an access semaphore */
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for (i = ICH_SEMATIMO / ICH_CODECIO_INTERVAL; i-- &&
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bus_space_read_1(sc->iot, sc->aud_ioh, ICH_CAS) & 1;
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@ -615,9 +592,11 @@ auich_reset_codec(void *v)
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for (i = 500000; i-- &&
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!(bus_space_read_4(sc->iot, sc->aud_ioh, ICH_GSTS) & ICH_PCR);
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DELAY(1)); /* or ICH_SCR? */
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if (!sc->sc_ignore_codecready && (i <= 0))
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#if 0
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if (i <= 0)
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printf("%s: auich_reset_codec: time out\n",
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sc->sc_dev.dv_xname);
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#endif
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}
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int
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