* if the driver hasn't been properly initialized, spin for a bit in wait_fifo()
rather than try to access the local0 status register.
* allow interrupt sharing (from Steve Rumble; necessary for IP20 glass TTY
support).
* fills seem to be broken. Avoid filling large vertical regions; instead,
attempt to break it up into managable chunks. This doesn't work perfectly
either, so clear the screen row-by-row (which does work).
* Characters are now right-side-up
* the driver now uses screen coordinates properly.
With the exception of column erases (which fall prey to the fill issue), the
driver is now usable.
to all GENERIC-like kernel config files where SYSV* options were already
present (commented out if the SYSV* options are commented out).
Fix lib/25897 and lib/25898.
same interrupt, and something isn't quite right with the mace interrupt
dispatcher. Disable for now.
Pointed out by Tillman Hodgson and confirmed by ozone on port-sgimips.
driver. Still some issues:
* framebuffer setup seems incomplete. Some drawing primitives work 100%
of the time, while others fail one in ten tries. Perhaps my board is
slightly broken, as the exact model as probed by ARCS seems to shift
between Elan and XS24 from time to time.
* characters are drawn bottom-up rather than top-down (as the wsfont
definitions expect).
drivers that attach to it. This allows for other host interface chips
that use the same keyboards and mice, such as the ones in the ARM
IOMD20, ARM7500, and SA-1111. The PC-compatible driver is still
called pckbc(4), and the new abstraction layer is "pckbport", so the
child devices have moved from sys/dev/pckbc to sys/dev/pckbport, which
also contains some code shared between all host controllers. To avoid
incompatibility, pckbdreg.h is still installed in
/usr/include/dev/pckbc.
In theory, this shouldn't cause any behavioural changes in the drivers
concerned. Thy just use rather more function pointers than before. Tested
on i386 and (with a new host driver) acorn32. Compiled on several other
affected architectures.
to only call pckbc_machdep_cnattach() if this is present. This allows
pckbc_machdep_cnattach() to be omitted entirely on most ports, where it only
returns ENXIO anyway.
The devices with this attribute at the moment are pc(4) on i386 and bebox, and
pckbc on sparc, where pckbc_machdep_cnattach() mysteriously returns 0 rather
than ENXIO.
* detect and store vc2 revision. This is (likely) the important factor in
determining the proper cursor offset, so add a bit of logic that does the
right thing on my revision 0 vc2. This will have to be determined
empirically, revision by revision.
* take a stab at detecting framebuffer depth. SGI does it quite differently,
but their algorithm doesn't work, so we'll do it along the same lines as
linux.
* implement newport_mmap() for use by X. The necessary xsrc commits have been
made (with the notable exception of the config/cf changes, which probably
shouldn't go in until 4.4.0 has been imported).
* Add resolution and depth variables to softc (for use in X driver, although
depth detection is currently problematic),
* Store more information about various chip revisions,
* Implement ioctls to help the X driver detect device presence and geometry.
* lpt device is defined in MI place (dev/ppbus/files.ppbus), dev/ic/lpt.c
is included there too; dev/ic/lpt.c is not included if ppbus is
configured or if there is alternative platform lpt (like for pc532)
* g/c MD lpt definitions and custom puc/upc attachments,
glue moved to conf/files and dev/pci/files.pci respectively; remove
device lpt definition from dev/isa/files.isa
* add ppbus parport attribute, atppc device attachments, adjust plip and lpt
glue
interrupts and timer calibration yet is also attached at mainbus).
Introduce the INDY_R4600_CACHE config option, which more accurately describes
the code enabled by this option.
This renders #ifdef IPxx completely obsolete, thus we theoretically can unify
the GENERIC files if a workable load address relocation scheme can be found.
mace devices to their own mace/ directory. Alter conf/files.sgimips to
reflect this change in a sane manner (i.e., pull in dev/files.dev and
mace/files.mace when appropriate).
At the same time, allow crime_intr_establish() to fall through to
mace_intr_establish(). mace devices now call cpu_intr_establish().
* move all device-specific bitbanging to the device drivers in question --
i.e., the ip32 init code doesn't access the CRIME registers directly but
instead trusts the CRIME driver to DTRT. machdep.c is cleaner thereby.
* introduce int.c, which handles the interrupt-controller goo formerly
in ip2x.c.
* unify the CPU interrupt handler, with CRIME, INT2, and the various timer
handlers hooked in via pointers in the platform struct.
* eliminate ip2x.c and ip32.c. After the interrupt handler cleanup, the
actual platform-dependent code was so minimal (rev identification, mask level
initialization) that it made sense to move it into machdep.c
* "#ifdef DEBUG printf("foo"); #endif" becomes aprint_debug.
Tested on my ip22 and ip32. Discussed with pooka@, rafal@.
The recommended workaround is a 5-10ms delay before and after accesses.
Therefore, move the affected bus_space_* operations from bus.h to bus.c
and special-case MACE accesses.
CRIME accesses are not affected, so introduce SGIMIPS_BUS_SPACE_CRIME and
use it as the CRIME tag.
My ip32 seems a little bit happier with this change, and my ip22 didn't
notice the change.
fit inside one memory chunk.
Leave 1 page before kernel untouched as that's where our initial kernel
stack before we switch to proc0 stack is (fixes boot problems on my Indy
with small kernels).
virtual memory reservation and a private pool of memory pages -- by a scheme
based on memory pools.
This allows better utilization of memory because buffers can now be allocated
with a granularity finer than the system's native page size (useful for
filesystems with e.g. 1k or 2k fragment sizes). It also avoids fragmentation
of virtual to physical memory mappings (due to the former fixed virtual
address reservation) resulting in better utilization of MMU resources on some
platforms. Finally, the scheme is more flexible by allowing run-time decisions
on the amount of memory to be used for buffers.
On the other hand, the effectiveness of the LRU queue for buffer recycling
may be somewhat reduced compared to the traditional method since, due to the
nature of the pool based memory allocation, the actual least recently used
buffer may release its memory to a pool different from the one needed by a
newly allocated buffer. However, this effect will kick in only if the
system is under memory pressure.
- hpc1_hdd_{ctl,bufptr} and hpc3_hdd_{ctl,bufptr} are
established in hpcreg.h. All references to these fields
are updated with the exception of if_sq: (haltwo,
hpcdma). This makes reading the code and spotting bugs
easier.
- hpcdma.c was applying EOCHAIN to the wrong descriptor
word for the hpc1 case.
- I added scsi_max_xfer to the abstraction layer, and it
allows some crusty #defines in wdsc.c to be removed.
hpc1 now doesn't waste descriptors as it once did.
- hpcreg.h was updated to reflect the lack of XMITDONE
bit in hpc1. HPC1_REV15 added for a test in hpc.c
- hpc.c now verifies HPC1 revisions (1.0 vs 1.5) and
prints the output a little prettier ;)
- power interrupts shouldn't establish on non-IP22
platforms.
divergence between HPC revision 1.5 and revision 3.
The wdsc driver has been updated to reflect this layer (and may now work on
IP20). The sq driver needs a bit more work before it can be committed.
routine, as IP20 does not possess an IOC. This will eventually be moved into
a dedicated IOC driver that attaches its peripherals as children, but the
changes involved are too intrusive right now.
zs_get_chan_addr() to reflect this.
XXX hardcoded addresses are quite distasteful. This should be passed in
through consinit() -- to avoid conflicts with Ilpo's soon-to-be-committed
framebuffer driver, I'll hold off until his code hits the tree.
