The brokenness is revealed sporadorically by memory usage on runtime.
- Avoid Vr4100 incompatibilty by making sure to retain default pgMask
value for TLB invalidation routines.
Fix regress/lib/libc/ieeefp/except for MIPS. Newer FPE handling code
did not generate SIGFPE, but always SIGILL. Add this back to the
assembly code. The QED 5231 requests the kernel emulates some of
the conditions that generate an SIGFPE, but when the emulation code
did a ctc1 to fsr with an exception the kernel got a FPE in kernel mode.
Fix this by saving the fp regs earlier, then saving the new FSR in
the context. This allows the FSR value to be seen by the SIGFPE
handler.
Add fp emulation for 8 mips2 fpu instructions to handle exceptions
(round.w.fmt, trunc.w.fmt, ceil.w.fmt, floor.w.fmt). This lets
perl5 run when compiled -mips2.
ASID#0 is reserved for pmap0 shared between proc0 and kthreads,
and every TLB for KSEG2 has G (global) bit to have wildcard match
regardless of the process' ASID. MIPS1 would flush TLBs belong
to user spaces upon ASID generation bump. Change for MIPS3 is
to be done.
uvm_page_init() has completed, add a boolean uvm.page_init_done,
and test against that. Use this same boolean (rather than
pmap_initialized) in pmap_growkernel() to determine if we are
being called via uvm_page_init() to grow the kernel address space.
This fixes a problem on some i386 configurations where pmap_init()
itself was needing to have the kernel page table grown, and since
pmap_initialized was not yet set to TRUE, pmap_growkernel() was
choosing the wrong code path.
Fix tested by Havard Eidnes.
half-baked and resulted in one superfluous ASID bump if new pmaps
are created when pmap_asid_generation > 0. Need to initialize pmap
fields correctly.
Yet, this possibly might not be the perfect solution. If one
process bumped pmap_asid_generation _after_ a new pmap was created
and initialized with then-current pmap_asid_generation value. In
that case, the new pmap would have another (superfluous) ASID bump
when 2nd (not 1st) CPU tick is assigned. I'm not sure if this case
would happen.
Have pmap_max_asid variable to hold the maximum number of ASID
(TLBpid) supported by processor anticipating the possible runtime
cost of ((CPUISMIPS3)? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS).
ALPHA; mips1_TBIA, mips1_TBIAP, mips1_TBIS.
- Make sure TBIA and TBIAP ops to have an argument for the size of TLB
which varies across even for MIPS1 implementations.
- Nuke the unused cpu_isa field from processor personality list.
- XXX XXX XXX
it's less-than-optimal and likely a mistake to have TLBUpdate().
It's costy to try to invalidate a single TLB entry whenver a certain
PTE is going to be modified by traversing the entire TLB looking
for the modified PTE because the PTE in question is not in TLB in
most cases. ASID bump could do the invalidation smartly. Solution
is planned for now.
was used for debugg'n purposes which only make senses on particular
hardware configurations and has never been intended to extend pagesize
of NetBSD/mips.
* Remove the casts to vaddr_t from the round_page() and trunc_page() macros to
make them type-generic, which is necessary i.e. to operate on file offsets
without truncating them.
* In due course, cast pointer arguments to these macros to an appropriate
integral type (paddr_t, vaddr_t).
Originally done by Chuck Silvers, updated by myself.
(which disables the interrupts) is *not* a good idea. k0 (and k1) is used
by the kernel code such as the TLB miss handler, and the interrupt entry.
If an interrupt occurs after loading k0 and before the SR gets interrupts
disabled, k0 will be clobbered and when used to load the PC on exit from
the exception handler, results in various hangs and crashes.
don't stomp on the return address in k0. Also, don't need to account
for any load delays, as the last register restored (gp) isn't used in
the subsequent instruction.
Shuichiro URATA <ur@a-r.org> makes kernel softfloat emulation code.
http://www.a-r.org/~ur/softfloat1116.diff.gz
is Patch for
sys/arch/mips/conf/files.mips
sys/arch/mips/mips/fp.S
sys/arch/mips/mips/fpemu.c
sys/arch/mips/mips/genassym.cf
sys/arch/mips/mips/locore.S
sys/arch/mips/mips/mips_machdep.c
sys/arch/mips/mips/process_machdep.c
sys/arch/mips/mips/trap.c
sys/arch/mips/mips/vm_machdep.c
After apply this patch,pmax package binary works on hpcmips!
Use flags (formerly access_type) to set page reference/modified status.
Don't use the PG_CLEAN flag from the UVM when checking to see if a
writeable page has been marked as modified.
When updating page status to modified from the UTLBmiss handler, set
the referenced bit in addition to the modified bit.
Page mod/ref status is stored in the pv header, and needs to be copied to
the following entry when removing the head entry, otherwise the status
will be lost (oops!).
Move the common MIPS3 cache flush into pmap_remove_pv() and eliminate the
unnecessary testing of the return value when only compiled for MIPS1.
If the pv entry had the cache inhibited, and we remove the last cache index
alias conflict, restore caching on the mappings for that entry.
Eliminate possible extra cache flushing inherited from the pica pmap: it
was doing the flush when the head entry was being removed - not just the last
entry. Now the flush is done only when the last mapping has been removed.
Also make sure the secondary cache gets flushed [MIPS3 cache flushing needs
to be re-thought/re-done someday].
Update comment for pmap_remove_pv() to reflect these changes.
original debug output was printing the argument to pmap_create(), but
pmap_create() no longer has an argument. The incorrect change now prints
an un-initialized pointer. Change to just print out the function name.
cache. With secondary cache, the CPU will detect cache coherency errors
and the Virtual Coherency Exception handler will flush the appropriate
cache lines to maintain cache coherency. This allows much better
performance than inhibiting the cache for the entire page. This is
very noticable when shared library mappings occur with incompatible
mappings, since there's a very likely chance the mappings will remain
for long periods of time. Systems without secondary cache will still
have the cache inhibited, so there will still be performance issues if
shared libraries don't get mmaped() on correct memory alignments.
This fixes the current problems on DECstations using the R4x00 getting
coredumped programs.
Support VR4100.
Support 16KB page.
Support CPU without FPU.
Fix virtual alias problem(physio() case).
[new options]
options MIPS3_4100 /* VR4100 core */
options MIPS_16K_PAGE /* enable kernel support for 16k pages */
options SOFTFLOAT /* No FPU; avoid touching FPU registers */
big-endian. i386, pc532 and vax still include <machine/byte_swap.h>
and define macros for the {n,h}to{h,n}*() functions. mips also
defines some endian-independent assembly-code aliases for unaligned
memory accesses.
in kernel mode after master interrupt (MIPS_SR_INT_IE) disabled. Tons
of appreciation for Noriyuki Soda and Masanari Tsubai for almost full
time help to spot of the issue.
- remove "need-flag" for mac68k esp driver, as it is not used in anywhere
and conflicts with IPsec ESP header.
This should be the only MD change in IPv6 support, except kernel config file.
Very sorry if you have any compilation problem with it (I believe it is okay).
If your favorite arch is not included in here, please add a
call to ip6intr() from softintr handle.
nisimura