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1214 Commits

Author SHA1 Message Date
manu
2e2ba05d0d Moved errno translation so that errno get translated correctly in any case, 
and so that EJUSTRETURN and ERESTART get proprely reported.
 2002-03-28 18:48:31 +00:00
simonb
4a1086db83 There's 8 interrupt_status_N registers, not 7. 2002-03-28 12:49:55 +00:00
simonb
de2d1df3a9 Remove the comment that says this is for PCI busses only. 2002-03-23 14:20:41 +00:00
simonb
8e5ab10b05 Add generic chipset memory and I/O "bus" functions for mips, based on 
algor/pci/pci_alignstride_bus_{io,mem}_chipdep.c.
 2002-03-23 14:19:18 +00:00
chs
fb88d3b0ba add missing cache flushes in pmap_protect(). fixes PR 15965. 2002-03-20 02:50:19 +00:00
simonb
267b8c65f5 Define all CPU types if _LKM is defined; fixes problems building LKM's 
as noted by FUKAUMI Naoki on port-mips.
 2002-03-19 00:53:46 +00:00
simonb
91785659ba Generic PCI/ISA machdep headers for mips; copied from the algor port. 2002-03-18 03:08:09 +00:00
simonb
7e2ca5e1a8 Copy the algor bus_dma.c for use as a generic bus_dma implementation for 
other MIPS ports.
 2002-03-18 02:32:54 +00:00
simonb
e64d2d9708 Oops, balance #ifdef/#endif _KERNEL. 2002-03-18 01:01:54 +00:00
simonb
d9aac5ef07 Add generic MIPS bus_space and bus_dma headers; these are a straight 
split of the algor <machine/bus.h>.
 2002-03-18 00:32:21 +00:00
manu
c51e325123 Replaced PS_STRINGS by p->p_psstr 2002-03-17 20:54:09 +00:00
simonb
9be5709e65 Fix some whitespace/indentation niggles. 2002-03-17 07:38:28 +00:00
simonb
17162f3d40 Add R4400 reg 0x60 to the MIPS CPU table. 
From PR port-mips/15894 from Thilo Manske.
 2002-03-13 13:18:58 +00:00
simonb
22db14d9e1 All the mips ports had an identical procfs_machdep.c, so use a common 
file under arch/mips/mips.
 2002-03-13 02:55:10 +00:00
uch
552fdb7e1b make this compile and work with MIPS3_5900. 2002-03-11 16:39:39 +00:00
thorpej
a180cee23b Pool deals fairly well with physical memory shortage, but it doesn't 
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map).  Try to deal with this:

* Group all information about the backend allocator for a pool in a
  separate structure.  The pool references this structure, rather than
  the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
  to become available, but will still fail if it cannot callocate KVA
  space for the pages.  If this happens, carefully drain all pools using
  the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
  some pages, and use that information to make draining easier and more
  efficient.
* Get rid of PR_URGENT.  There was only one use of it, and it could be
  dealt with by the caller.

From art@openbsd.org.
 2002-03-08 20:48:27 +00:00
tsutsui
3c8b0446fe Change type of dumpmag to u_int32_t since it is actually 
a 32bit unsigned magic number.
As per discussion on tech-kern, and fixes port-sparc64/11949.
 2002-03-06 13:10:18 +00:00
simonb
1c904f9d33 Use MIPS_PHYS_TO_KSEG1 instead of cfe's PHYS_TO_K1 macro. 2002-03-06 09:32:04 +00:00
simonb
2bf916e97d Implement a clkread() function for microtime() using a multu/mfhi 
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
 2002-03-06 07:47:57 +00:00
simonb
feb24029e7 Add the offset of ci_divisor_delay in struct cpu_info. 2002-03-06 07:32:15 +00:00
simonb
78c9211fca Add a field for the reciprocal of the divisor delay for use by microtime. 2002-03-06 07:31:38 +00:00
simonb
3fe666190f Wrap long line and remove a bogus XXX comment. 2002-03-06 03:25:09 +00:00
simonb
2c68c156c5 Only include <sys/exec_ecoff.h> if EXEC_ECOFF is defined. 
Note that ELF is mandatory.
 2002-03-06 00:22:09 +00:00
simonb
3ab34324e9 Remove a few unneeded include files. 2002-03-06 00:05:06 +00:00
simonb
1b5ddfe411 Add support for the on-chip peripherals on the Broadcom SiByte SB1250 CPU 
and support routines for the Broadcom CFE (Common Firmware Environment).

This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
 2002-03-05 23:46:40 +00:00
simonb
f1dbc97679 Not used anymore. 2002-03-05 16:08:55 +00:00
simonb
811ee92532 Add support for MIPS32 and MIPS64 architectures: 
- Build mips3/5900/32/64 support subroutines.
 - Move arch/mips/mips/fp.S to central location.
 - Move NOFPU to opt_cputype.h.
 2002-03-05 16:08:00 +00:00
simonb
f340c57568 Values related to the MIPS32/MIPS64 Privileged Resource Architecture 
(from Broadcom Corp).
 2002-03-05 16:07:10 +00:00
simonb
9ac7c86a0f Adjust for 5900 include file changes. 2002-03-05 16:06:04 +00:00
simonb
3f2f4c9bf6 r5900_vector_init() is in mips_machdep.c now. 2002-03-05 16:05:26 +00:00
simonb
dd756c0ca5 Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some 
content no longer needed.
 2002-03-05 16:04:57 +00:00
simonb
fcdc111c1a Cosmestic changes (more like the mips3+ code). 2002-03-05 16:03:22 +00:00
simonb
c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info 
is in the table in mips_machdep.c now.
 2002-03-05 16:02:48 +00:00
simonb
c6bcfb2589 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Bump the Sysmap size a little for large-memory machines.
XXX: still need work, especially in pmap_procwr().
 2002-03-05 16:01:25 +00:00
simonb
0f9c00fc2e Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - ANSIfy.
 2002-03-05 15:57:20 +00:00
simonb
fa9c08ab16 Remove HPCMIPS_FLUSHCACHE_XXX debug code. 
Remove old unused exception frame unwind code.
Change a MIPS3 check to a MIPS3_PLUS check.
ANSIfy.
 2002-03-05 15:55:41 +00:00
simonb
278bfc1c02 Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:54:33 +00:00
simonb
351c1c16a6 Add support for MIPS32 and MIPS64 architectures: 
- Use a table-driven CPU detection algorithm instead of multiple
   case statements.
 - Add MIPS32/64 feature detection using the architected CP0 registers
   (from Broadcom Corp).
 - Call MD mips_machdep_cache_config() function if
   __HAVE_MIPS_MACHDEP_CACHE_CONFIG is defined - used to set up the
   L2 cache on some ports.
 2002-03-05 15:53:00 +00:00
simonb
ba8e2e82e4 Add support for MIPS32 and MIPS64 architectures: 
- Remove all mmu-related code that may use 32 register on mips32-style
   implementatios and move them to mipsX_subr.S - which is then included
   from mips{3,32,64,5900}_subr.S with various control defines enabled.
 - Remove local cache instruction flags
 - Add badaddr64 (from Broadcom Corp).
 2002-03-05 15:50:59 +00:00
simonb
9ed4fd257f Change a MIPS3 check to a MIPS3_PLUS check. 
XXX: I'm not 100% sure of the intent of this code - it would seem that
 it needs a run-time check of CPU ISA to be completely correct...
 2002-03-05 15:48:31 +00:00
simonb
d62813603c Check userland address and address alignent as two separate checks. 
Fix for when mips_reg_t is 64-bits.
ANSIfy.
 2002-03-05 15:46:51 +00:00
simonb
fe86ad150e Change MIPS3 checks to MIPS3_PLUS checks (XXX - still bogus!). 2002-03-05 15:44:40 +00:00
simonb
c9a3bd8900 Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 - Add a command to dump cp0 state.
 2002-03-05 15:43:25 +00:00
simonb
9b785c48f3 Cache ops for MIPS32/64 cpus. 2002-03-05 15:42:50 +00:00
simonb
0446046fde Add MIPS32/64 cache setup code (from Broadcom Corp). 2002-03-05 15:42:21 +00:00
simonb
cae6e0e516 Prototypes for MIPS32/64 cache ops. 2002-03-05 15:41:48 +00:00
simonb
0ff59237ca Change a MIPS3 check to a MIPS3_PLUS check (XXX - still bogus!). 2002-03-05 15:41:14 +00:00
simonb
01422aae5c Add support for MIPS32 and MIPS64 architectures: 
- move away from using CPUISMIPS3; use MIPS_HAS_CLOCK instead.
 2002-03-05 15:40:10 +00:00
simonb
1d05db445d Add support for MIPS32 and MIPS64 architectures: 
- Move away from using CPUISMIPS3; use MIPS_HAS_R4K_MMU instead.
 2002-03-05 15:39:31 +00:00
simonb
934c4ba555 Add support for MIPS32 and MIPS64 architectures: 
Remove the unused PSL_USERCLR and BASEPRI macros.
 2002-03-05 15:38:33 +00:00