Commit Graph

1431 Commits

Author SHA1 Message Date
thorpej
65fdfe7d64 Add TA0-TA3 register indices. 2002-11-04 04:24:48 +00:00
thorpej
abaff8e1c6 t4-t7 -> ta0-ta3 2002-11-04 04:06:51 +00:00
thorpej
3e54f426e0 Rearrange mips_pagecopy() and mips_pagezero() for N32/LP64.
XXX Does not yet use the correct reg names for new-ABI.
2002-11-04 04:04:32 +00:00
thorpej
1bf923d5f3 Add N32 register vars. 2002-11-04 03:46:18 +00:00
thorpej
aa2b9a65fc Add SGI-compatible ta0-ta3 register names. These allow one to write
asm code which can be built easily in old-ABI and new-ABI environemnts.

In old-ABI, they map to t4-t7, and in new-ABI, they map to a4-a7.  This
means that t0-t3,ta0-ta3,t8,t9 are available in both ABIs.

Because ta0-ta3 overlap with arg regs (albeit arg slots which are usually
unused), they should be used only if t0-t3,t8,t9 isn't enough.
2002-11-04 03:38:32 +00:00
thorpej
bae541911c Add N32/N64 reg names. 2002-11-04 03:30:32 +00:00
thorpej
15d3b348c9 Add LP64 limits. 2002-11-03 20:02:39 +00:00
thorpej
9f9d6d33f4 Add LP64 types, limits, formats. 2002-11-03 19:55:23 +00:00
thorpej
f8dceffac5 Add LP64 macros. 2002-11-03 19:24:55 +00:00
thorpej
c88320f8d7 Add LP64 types. 2002-11-03 19:22:00 +00:00
thorpej
16084f1873 Add _LP64 types. 2002-11-03 17:43:07 +00:00
thorpej
c5adb2880e In the _MIPS_PADDR_T_64BIT case, only use "unsigned long long" if _LP64
is not defined.
2002-11-03 17:35:32 +00:00
nisimura
ad5b782866 Retire __HAVE_MD_RUNQUEUE from MD types.h and remove
setrunqueue/remrunqueue from locore.S.  C codes are
compiled a bit shorter and provide better DIAGNOSTICs.
2002-11-03 13:47:34 +00:00
nisimura
5a63303fc1 Add two PRiD values.
- 0x55 for NEC Vr5500.  ISA might be MIPS64.
- 0x38 for Toshiba TX79.  This has thirty-two 128bit GPRs while
maintaining 32bit only virtual address space.  Any of pointer related
registers have 32bit.
2002-11-03 13:16:11 +00:00
thorpej
3d93c95dc8 Make register_t == long long for N32, and == long for everthing else.
Use register_t in label_t.
2002-11-02 02:45:22 +00:00
thorpej
3517ae5f6a Define N32/N64 register usage. 2002-11-02 02:00:17 +00:00
jdolecek
e0cc03a09b merge kqueue branch into -current
kqueue provides a stateful and efficient event notification framework
currently supported events include socket, file, directory, fifo,
pipe, tty and device changes, and monitoring of processes and signals

kqueue is supported by all writable filesystems in NetBSD tree
(with exception of Coda) and all device drivers supporting poll(2)

based on work done by Jonathan Lemon for FreeBSD
initial NetBSD port done by Luke Mewburn and Jason Thorpe
2002-10-23 09:10:23 +00:00
chs
b79663cf62 eliminate PT_ENTRY_NULL in favor of plain old NULL. 2002-10-14 05:11:21 +00:00
simonb
b1a30609f9 Install the kernel linker script in /usr/lkm/ldscript so that modload(8)
works without needing to resort to -A abuse.  LKMs work cleanly on MIPS
now.
2002-10-10 01:59:29 +00:00
chs
993948e989 count executable image pages as executable for vm-usage purposes.
also, always do the VTEXT vs. v_writecount mutual exclusion
(which we previously skipped if the text or data segment was empty).
2002-10-05 22:34:02 +00:00
thorpej
89bf5a8f8e Add trailing ; to CFATTACH_DECL. 2002-10-02 15:52:22 +00:00
thorpej
c5e91d447d Use CFATTACH_DECL(). 2002-10-02 04:55:47 +00:00
thorpej
c4cbfcf060 Use CFATTACH_DECL(). 2002-10-01 02:54:11 +00:00
thorpej
f818766afe Declare all cfattach structures const. 2002-09-27 20:31:45 +00:00
provos
0f09ed48a5 remove trailing \n in panic(). approved perry. 2002-09-27 15:35:29 +00:00
thorpej
6c88de3b53 Introduce a new routine, config_match(), which invokes the
cfattach->ca_match function in behalf of the caller.  Use it
rather than invoking cfattach->ca_match directly.
2002-09-27 03:17:40 +00:00
thorpej
d1ad2ac4f2 Rather than referencing the cfdriver directly in the cfdata entries,
instead use a string naming the driver.  The cfdriver is then looked
up in a list which is built at run-time.
2002-09-27 02:24:06 +00:00
thorpej
274c086b22 Remove <sys/map.h> 2002-09-26 18:54:30 +00:00
simonb
63096043b3 Use "#define\t" instead of "#define ". 2002-09-22 08:30:56 +00:00
chs
c081614ea2 it really helps to get the stub right before cutting + pasting it 27 times.
alas, I did not.  doh.
2002-09-22 07:53:39 +00:00
chs
55e1f79335 add pmap_remove_all() hook (empty on most platforms so far). 2002-09-22 07:17:08 +00:00
gmcgarry
45d41256f3 Update for cpu_switch() prototype change. No functional change. 2002-09-22 05:40:35 +00:00
gmcgarry
dca80f08fd Add __HAVE_MD_RUNQUEUE flag for MD code to override MI run queue primitives. 2002-09-22 04:11:32 +00:00
manu
80ee637534 - Introduce a e_fault field in struct proc to provide emulation specific
memory fault handler. IRIX uses irix_vm_fault, and all other emulation
use NULL, which means to use uvm_fault.

- While we are there, explicitely set to NULL the uninitialized fields in
struct emul: e_fault and e_sysctl on most ports

- e_fault is used by the trap handler, for now only on mips. In order to avoid
intrusive modifications in UVM, the function pointed by e_fault does not
has exactly the same protoype as uvm_fault:
int uvm_fault __P((struct vm_map *, vaddr_t, vm_fault_t, vm_prot_t));
int e_fault __P((struct proc *, vaddr_t, vm_fault_t, vm_prot_t));

- In IRIX share groups, all the VM space is shared, except one page.
This bounds us to have different VM spaces and synchronize modifications
to the VM space accross share group members. We need an IRIX specific hook
to the page fault handler in order to propagate VM space modifications
caused by page faults.
2002-09-21 21:14:54 +00:00
ragge
b3abfee038 Do not include <sys/clist.h>, it's not used in NetBSD at all. 2002-09-19 10:37:59 +00:00
gmcgarry
a2e5c0f036 Bring down from nathanw_sa branch. 2002-09-16 07:00:43 +00:00
simonb
7f4e82e47b Add CPU_MIPS_DOUBLE_COUNT for the TX49xx cpus. 2002-09-13 01:27:46 +00:00
simonb
f41231cffc Fix the order of the CPU revision and company options fields in the cpu
table for the Alchemy CPUs; successfully recognises an Au1500 now.
2002-09-09 03:42:04 +00:00
simonb
54ef88d289 In the idle functions, set curproc to NULL and (#ifdef LOCKDEBUG) call
sched_unlock_idle before enabling interrupts.  LOCKDEBUG kernels now
boot successfully.

Thanks to Chris Gilbert for helping fix this.
2002-09-09 02:32:38 +00:00
simonb
378a5c4c85 Include "opt_lockdebug.h" here to #ifdef LOCKDEBUG actually does something. 2002-09-09 01:03:10 +00:00
gehenna
77a6b82b27 Merge the gehenna-devsw branch into the trunk.
This merge changes the device switch tables from static array to
dynamically generated by config(8).

- All device switches is defined as a constant structure in device drivers.

- The new grammer ``device-major'' is introduced to ``files''.

	device-major <prefix> char <num> [block <num>] [<rules>]

- All device major numbers must be listed up in port dependent majors.<arch>
  by using this grammer.

- Added the new naming convention.
  The name of the device switch must be <prefix>_[bc]devsw for auto-generation
  of device switch tables.

- The backward compatibility of loading block/character device
  switch by LKM framework is broken. This is necessary to convert
  from block/character device major to device name in runtime and vice versa.

- The restriction to assign device major by LKM is completely removed.
  We don't need to reserve LKM entries for dynamic loading of device switch.

- In compile time, device major numbers list is packed into the kernel and
  the LKM framework will refer it to assign device major number dynamically.
2002-09-06 13:18:43 +00:00
gmcgarry
1a8058823b RAS support for MIPS. Tested on R3000. 2002-08-28 08:34:06 +00:00
simonb
993a94e6bc Add the Toshiba TX4927 CPU. 2002-08-28 02:09:29 +00:00
simonb
0702d44ac5 Fix printf format string for the EXTENT_DEBUG case. 2002-08-19 12:03:48 +00:00
simonb
771cbe3e84 Remove CPU_MIPS_DOUBLE_COUNT for the MIPS 20Kc - it's cycle counter runs
at the normel CPU frequency.
2002-08-19 12:03:04 +00:00
simonb
7e0228bbc3 Update to rev 1.48 from Algorithmics; adds BONITO64 register definitions. 2002-08-18 16:00:33 +00:00
simonb
fd2320f396 Issue a dummy read after a write to the BONITO_PCIMAP_CFG register to
make sure the write is posted; needed to keep the BONITO64 happy.
2002-08-18 15:57:55 +00:00
briggs
0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
2002-08-07 05:14:47 +00:00
shin
b0d22e8404 fix CPU_ROOT_DEVICE implementation. 2002-08-06 06:54:36 +00:00
shin
a59d490375 * add CPU_MIPS_NO_LLSC to Toshiba TX3912, TX3922, TX3927.
* fix mips_has_llsc calculation logic.
2002-08-05 13:02:40 +00:00
shin
2f33f11745 ++CPU_MAXID for CPU_LLSC. 2002-08-05 13:00:47 +00:00
simonb
f068458085 The TX79 core in the R5900 doesn't support LL/SC.
XXX: Others in this table will need to be updated.
2002-08-05 02:18:43 +00:00
simonb
fef76c7e26 Use a __HAVE_BOOTINFO_H define to check for bootinfo support instead of
speading port names in arch-dependant code.
2002-08-05 02:13:14 +00:00
gmcgarry
460c8c3adc mipsco and sgimips also implement bootinfo, but didn't provide
the CPU_BOOTED_KERNEL sysctl variable.
2002-08-04 03:16:19 +00:00
gmcgarry
7470337484 Move LLSC feature test for mips1 to cputab[]. 2002-08-04 02:27:51 +00:00
gmcgarry
617f58fb55 Add sysctl variable to represent native CPU support for LL/SC instructions. 2002-08-04 01:47:15 +00:00
gmcgarry
886e32d355 mips1 doesn't have native LL/SC instructions. 2002-08-04 01:43:03 +00:00
gmcgarry
3647e0d293 Merge cpu_sysctl() for all mips ports, based on powerpc and m68k precedent.
For now, only pmax implements CPU_BOOTED_KERNEL.  Need to revisit.
2002-08-04 01:41:23 +00:00
simonb
e5a27ab142 Sync bcm1250 headers with cfe-1.0.32. 2002-07-31 06:26:24 +00:00
simonb
e9dfdd9b2e Add support for the watchdog timers on the BCM1xxx parts. 2002-07-31 05:30:20 +00:00
simonb
314a0f00d1 Fix the mask for the watchdog init and count registers. 2002-07-30 23:10:04 +00:00
simonb
c38f2b0214 Remove some debug code accidently left in. 2002-07-29 16:25:02 +00:00
simonb
223e50d28e Add a slightly modified dev/ic/com.c that supports the Alchemy
Semiconductor Au1x00 series on-chip UARTs.  Will be merged with
the original com.c driver once a few issues are tidied up.  Main
differences from a standard 16550 UART are:
 - separate rxdata and txdata registers
 - single 16-bit register for the clock divisor
 - "enable uart" register
2002-07-29 15:42:41 +00:00
simonb
ca42af5e80 Add support for the the Alchemy Semiconductor Au1x00 series on-chip
devices.  Currently the serial ports and ethernet MAC have working
drivers, and this has only been physically tested on the Au1000 CPU,
but these devices should work on the Au1100 and Au1500 CPUs too.
2002-07-29 15:39:11 +00:00
itojun
f8e5e9c295 be friendly with gcc-3.1.1 -O2, which takes advantage of ANSI C
pointer aliasing rule (gcc optimization/7427).  from tsubai, sync w/kame
2002-07-29 09:14:36 +00:00
simonb
328bb37293 Add support for detecting Alchemy Semiconductor CPUs. Alchemy use the
processor ID field to donote the CPU core revision and the company
options field do donate the SOC chip type, so we need to add an extra
field to the "pridtab" structure to identify these CPUs.
2002-07-26 00:43:54 +00:00
gmcgarry
2e0c7e68a5 Implement true LL/SC emulation. Mostly from Jason Thorpe in PR17548. 2002-07-21 05:47:51 +00:00
simonb
bfbb000051 White space nits, add a #endif comment. 2002-07-19 03:13:55 +00:00
gmcgarry
cc4037a913 Overhaul the emulation facility. We do this by:
- accumulating all emulation code (including floating-point) in one place
- steal MachFPInterrupt() back from SOFTFLOAT for use only with interrupts
  and traps from *real* FPUs
- introducing MachEmulateInst() as a common dispatch point for all
  emulated instructions
- cleaning up emulation dispatch in trap()

Also, while we're here, implement MIPS2 LL/SC/SYNC emulation for MIPS1.

Tested on r3k with and without SOFTFLOAT enabled.
2002-07-06 23:59:18 +00:00
thorpej
011d4d5f44 Add kernel support for having userland provide the signal trampoline:
* struct sigacts gets a new sigact_sigdesc structure, which has the
  sigaction and the trampoline/version.  Version 0 means "legacy kernel
  provided trampoline".  Other versions are coordinated with machine-
  dependent code in libc.
* sigaction1() grows two more arguments -- the trampoline pointer and
  the trampoline version.
* A new __sigaction_sigtramp() system call is provided to register a
  trampoline along with a signal handler.
* The handler is no longer passed to sensig() functions.  Instead,
  sendsig() looks up the handler by peeking in the sigacts for the
  process getting the signal (since it has to look in there for the
  trampoline anyway).
* Native sendsig() functions now select the appropriate trampoline and
  its arguments based on the trampoline version in the sigacts.

Changes to libc to use the new facility will be checked in later.  Kernel
version not bumped; we will ride the 1.6C bump made recently.
2002-07-04 23:32:02 +00:00
thorpej
bf7d5bca07 Eliminate 4 unused sigframe members. 2002-07-04 19:20:01 +00:00
simonb
a441a7dffa Remove some clocktick debug code. 2002-06-27 04:09:15 +00:00
simonb
7471732325 Add the 20Kc processor ID. 2002-06-27 03:43:45 +00:00
simonb
8e38e28f7f White space nits: space after a comma. 2002-06-24 05:52:28 +00:00
simonb
d4068eac65 Add 64MB and 256MB tlb page masks. 2002-06-24 05:46:47 +00:00
manu
d0c5097f05 Typo 2002-06-23 20:36:36 +00:00
simonb
4cf248e04b Fix tyop. 2002-06-17 22:48:45 +00:00
christos
3b50728cf4 MD systrace gluons. 2002-06-17 16:32:57 +00:00
simonb
4d304073f1 Add some ifdef's around the usage of mips_wait_idle; fixes builds for
playstations2 and MIPS1-only kernels.
Based on patch from Bill Squier.
2002-06-07 02:05:22 +00:00
simonb
e36c88d696 Introduce CHIP_ACCESSTYPE which (if defined) is used as the type for
performing the accesses, regardless of the size of the data type
requested.  Useful for chips which require fixed-width accesses to all
registers.

Cast arguments printed using %lx to u_long all the time, not just
sometimes.

Include a few extra files here so they don't need to be included by the
files that include this one.
2002-06-05 06:27:10 +00:00
simonb
8492ceb1ff White space nits. 2002-06-05 06:09:28 +00:00
simonb
db50a069f8 Remove an ELF-related comment that isn't needed any more. 2002-06-05 06:02:52 +00:00
simonb
2100183aff For the CP0 status register bit definitions- add the MX, PX and NMI bits
and rename TLB_SHUTDOWN and SOFT_RESET to TS and SR (the abbreviations
in the MIPS documentation).

XXX: this file really needs to be cleaned up one day...
2002-06-05 05:56:48 +00:00
thorpej
04076e5943 Make this work with an ISO C preprocessor. 2002-06-04 21:44:40 +00:00
thorpej
d941ddfee0 Don't use -traditional-cpp if HAVE_GCC3. 2002-06-04 21:39:09 +00:00
simonb
f4e42e7eb6 Add an extremely rough SMBus handler and RTC driver. This will be
cleaned up significantly when we have an MI SMBus framework, but at
least we can see the RTC on the swarm now.
2002-06-04 08:32:41 +00:00
simonb
9cc65a96d0 3 ports are now using the reciprocal count divisor code now, move it
to <mips/cpu.h>, and add MIPS_SET_CI_RECIPRICAL and MIPS_COUNT_TO_MHZ
macros to use it.
2002-06-04 05:42:41 +00:00
simonb
8b4906e391 Add prototypes for the 64-bit pagezero functions.
Bracket some function prototypes with #ifdef/#endif.
2002-06-03 01:51:05 +00:00
drochner
d2b9876081 move initialization of the "struct pglist" returned by uvm_pglistalloc()
from the calling code into uvm_pglistalloc() itself for consistency
and easier error handling
2002-06-02 14:44:35 +00:00
simonb
4cb13fbec6 There's two SMBuses in the BCM1250; list them both on the on-board device
list.
Get rid of some magic numbers.
2002-06-01 13:56:56 +00:00
simonb
51a91ebabb KNF; make some function static; other minor cleanups. 2002-06-01 13:55:48 +00:00
simonb
1e10b4d4ad Split USE_64BIT_FUNCTIONS into USE_64BIT_INSTRUCTIONS and
USE_64BIT_CP0_FUNCTIONS.
Add 64-bit pagezero function.
2002-06-01 13:52:23 +00:00
simonb
341ed8c0d3 Use CPU_MIPS_USE_WAIT and CPU_MIPS_NO_WAIT in the CPU table, and use
the generic name "mips_wait_idle" for the old function that had both
rm52xx_idle and mipsNN_idle entry points.
2002-06-01 13:45:45 +00:00
simonb
3611959ac8 Remove some unnecessary nops after some mfc0's. 2002-06-01 13:16:44 +00:00
simonb
cf5f852d1c Standardise on the name "MIPS_SR_BEV" instead of a couple of different
#defines for the same status bit.
2002-06-01 12:27:03 +00:00
simonb
5b5cc1ebb8 Add two new cpu capability flags: CPU_MIPS_USE_WAIT for CPUs that use a
"wait" instruction based cpu_idle(), and CPU_MIPS_NO_WAIT for specific
CPUs that don't use this (applicable to mips32/64 mainly).
2002-06-01 12:10:45 +00:00
simonb
d75c18b050 Use the current MIPS in_cksum for in4_cksum too. 2002-06-01 11:41:33 +00:00
thorpej
80f6433965 Fix printf format issues. 2002-05-31 21:09:03 +00:00
thorpej
dada8613e1 Let machine-dependent code specify how to enumerate the bus.
Currently, everyone uses pci_enumerate_bus_generic().
2002-05-15 19:23:51 +00:00
simonb
ada33c9eac Oops, remove an #endif leftover from the previous change. 2002-05-13 06:11:52 +00:00
simonb
c790dd34b6 Add a comment after an #endif to match up with an #ifdef. 2002-05-13 04:15:40 +00:00
simonb
ee2264c945 All MIPS ports have been ELF for a long time (most since they were
created); remove non-ELF assembly support.
2002-05-13 01:39:17 +00:00
rafal
13c470a169 R4600 and R5000 count registers count at half-cpu-speed as well. 2002-05-03 03:50:11 +00:00
simonb
fa61e6cd3b In the LOCKDEBUG case, call exit2() before sched_lock_idle() so
that the exitting process pointer in a0 doesn't get overwritten by
sched_lock_idle().
2002-04-25 06:55:53 +00:00
manu
33d1091e95 Removed the IRIX signal trampoline, which is useless now we use the signal
trampoline provided by IRIX libc.
2002-04-14 21:52:25 +00:00
manu
c56e133974 More comments on the new signal frame/trampoline 2002-04-13 10:52:59 +00:00
manu
5ee554064d Reworked IRIX signal delivery so that ucontext is used instead of sigcontext
when SA_SIGINFO is used. The IRIX process will hence find the expected
information using the third argument of the signal handler.

We do not provide code and siginfo yet.
2002-04-12 18:44:57 +00:00
manu
79166f2808 iAdded warning printtf just in case something calls the stubs functions here 2002-04-06 18:03:17 +00:00
simonb
2d7c87ebfb Add a "CPU_MIPS_DOUBLE_COUNT" flag for CPUs where the cp0 count register
ticks over at half the CPU clock speed, and set this flag for the known
CPUs with this behaviour.  Better names for this flag gratefully accepted!

Also adjust comment about known R4000/R4400 revisions.
2002-04-05 01:22:16 +00:00
simonb
fab269a0eb Backout the .sdata to .data change for now; this broke compiling of
hpcmips kernels.
2002-04-03 13:57:47 +00:00
simonb
2548187935 Don't make arch/mips/mips/mips_mcclock.c mandatory for all mips ports
with an mcclock - pmax is the only one currently using this.
2002-04-03 13:16:13 +00:00
simonb
ccc73cca48 Put a couple of variables in the data section, not the sdata section. 2002-04-03 04:04:31 +00:00
simonb
6fbaedb430 Use the new 2way mips{32,64} cache ops. 2002-04-03 03:55:07 +00:00
simonb
67fd901d75 Include 2way cache ops for mips{32,64} CPUs. 2002-04-03 03:51:00 +00:00
simonb
078e9477f0 Add prototype for badaddr64(). 2002-04-03 03:48:33 +00:00
simonb
85c30a703d Remove a commented-out debug printf. 2002-04-03 03:47:53 +00:00
manu
5f93fe2017 undef SYSCALL_SHIFT after using it so that it is possible to define both
COMPAT_IRIX and COMPAT_LINUX without getting warnings about SYSCALL_SHIFT
being redefined.
2002-04-01 21:06:21 +00:00
manu
2e2ba05d0d Moved errno translation so that errno get translated correctly in any case,
and so that EJUSTRETURN and ERESTART get proprely reported.
2002-03-28 18:48:31 +00:00
simonb
4a1086db83 There's 8 interrupt_status_N registers, not 7. 2002-03-28 12:49:55 +00:00
simonb
de2d1df3a9 Remove the comment that says this is for PCI busses only. 2002-03-23 14:20:41 +00:00
simonb
8e5ab10b05 Add generic chipset memory and I/O "bus" functions for mips, based on
algor/pci/pci_alignstride_bus_{io,mem}_chipdep.c.
2002-03-23 14:19:18 +00:00
chs
fb88d3b0ba add missing cache flushes in pmap_protect(). fixes PR 15965. 2002-03-20 02:50:19 +00:00
simonb
267b8c65f5 Define all CPU types if _LKM is defined; fixes problems building LKM's
as noted by FUKAUMI Naoki on port-mips.
2002-03-19 00:53:46 +00:00
simonb
91785659ba Generic PCI/ISA machdep headers for mips; copied from the algor port. 2002-03-18 03:08:09 +00:00
simonb
7e2ca5e1a8 Copy the algor bus_dma.c for use as a generic bus_dma implementation for
other MIPS ports.
2002-03-18 02:32:54 +00:00
simonb
e64d2d9708 Oops, balance #ifdef/#endif _KERNEL. 2002-03-18 01:01:54 +00:00
simonb
d9aac5ef07 Add generic MIPS bus_space and bus_dma headers; these are a straight
split of the algor <machine/bus.h>.
2002-03-18 00:32:21 +00:00
manu
c51e325123 Replaced PS_STRINGS by p->p_psstr 2002-03-17 20:54:09 +00:00
simonb
9be5709e65 Fix some whitespace/indentation niggles. 2002-03-17 07:38:28 +00:00
simonb
17162f3d40 Add R4400 reg 0x60 to the MIPS CPU table.
From PR port-mips/15894 from Thilo Manske.
2002-03-13 13:18:58 +00:00
simonb
22db14d9e1 All the mips ports had an identical procfs_machdep.c, so use a common
file under arch/mips/mips.
2002-03-13 02:55:10 +00:00
uch
552fdb7e1b make this compile and work with MIPS3_5900. 2002-03-11 16:39:39 +00:00
thorpej
a180cee23b Pool deals fairly well with physical memory shortage, but it doesn't
deal with shortages of the VM maps where the backing pages are mapped
(usually kmem_map).  Try to deal with this:

* Group all information about the backend allocator for a pool in a
  separate structure.  The pool references this structure, rather than
  the individual fields.
* Change the pool_init() API accordingly, and adjust all callers.
* Link all pools using the same backend allocator on a list.
* The backend allocator is responsible for waiting for physical memory
  to become available, but will still fail if it cannot callocate KVA
  space for the pages.  If this happens, carefully drain all pools using
  the same backend allocator, so that some KVA space can be freed.
* Change pool_reclaim() to indicate if it actually succeeded in freeing
  some pages, and use that information to make draining easier and more
  efficient.
* Get rid of PR_URGENT.  There was only one use of it, and it could be
  dealt with by the caller.

From art@openbsd.org.
2002-03-08 20:48:27 +00:00
tsutsui
3c8b0446fe Change type of dumpmag to u_int32_t since it is actually
a 32bit unsigned magic number.
As per discussion on tech-kern, and fixes port-sparc64/11949.
2002-03-06 13:10:18 +00:00
simonb
1c904f9d33 Use MIPS_PHYS_TO_KSEG1 instead of cfe's PHYS_TO_K1 macro. 2002-03-06 09:32:04 +00:00
simonb
2bf916e97d Implement a clkread() function for microtime() using a multu/mfhi
sequence using the reciprocal of the delay divisor to perform the
division.
Set the cp0 compare register so that it doesn't trigger interrupts and
reset the cp0 count register in the hardclock interrupt handler.
2002-03-06 07:47:57 +00:00
simonb
feb24029e7 Add the offset of ci_divisor_delay in struct cpu_info. 2002-03-06 07:32:15 +00:00
simonb
78c9211fca Add a field for the reciprocal of the divisor delay for use by microtime. 2002-03-06 07:31:38 +00:00
simonb
3fe666190f Wrap long line and remove a bogus XXX comment. 2002-03-06 03:25:09 +00:00
simonb
2c68c156c5 Only include <sys/exec_ecoff.h> if EXEC_ECOFF is defined.
Note that ELF is mandatory.
2002-03-06 00:22:09 +00:00
simonb
3ab34324e9 Remove a few unneeded include files. 2002-03-06 00:05:06 +00:00
simonb
1b5ddfe411 Add support for the on-chip peripherals on the Broadcom SiByte SB1250 CPU
and support routines for the Broadcom CFE (Common Firmware Environment).

This code is provided by the Broadband Processor Business Unit at
Broadcom Corp with minor updates by me.
2002-03-05 23:46:40 +00:00
simonb
f1dbc97679 Not used anymore. 2002-03-05 16:08:55 +00:00
simonb
811ee92532 Add support for MIPS32 and MIPS64 architectures:
- Build mips3/5900/32/64 support subroutines.
 - Move arch/mips/mips/fp.S to central location.
 - Move NOFPU to opt_cputype.h.
2002-03-05 16:08:00 +00:00
simonb
f340c57568 Values related to the MIPS32/MIPS64 Privileged Resource Architecture
(from Broadcom Corp).
2002-03-05 16:07:10 +00:00
simonb
9ac7c86a0f Adjust for 5900 include file changes. 2002-03-05 16:06:04 +00:00
simonb
3f2f4c9bf6 r5900_vector_init() is in mips_machdep.c now. 2002-03-05 16:05:26 +00:00
simonb
dd756c0ca5 Rename <mips/r5900/cpuregs.h> to <mips/r5900regs.h> and remove some
content no longer needed.
2002-03-05 16:04:57 +00:00
simonb
fcdc111c1a Cosmestic changes (more like the mips3+ code). 2002-03-05 16:03:22 +00:00
simonb
c5d34b4371 Remove the number of TLB entries for different rx39 CPUs - this info
is in the table in mips_machdep.c now.
2002-03-05 16:02:48 +00:00