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Fix the order of the CPU revision and company options fields in the cpu

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table for the Alchemy CPUs; successfully recognises an Au1500 now.
This commit is contained in:
simonb 2002-09-09 03:42:04 +00:00
parent eb0197ee71
commit f41231cffc
1 changed files with 8 additions and 8 deletions
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16
sys/arch/mips/mips/mips_machdep.c
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@ -1,4 +1,4 @@
/* $NetBSD: mips_machdep.c,v 1.148 2002/09/06 13:18:43 gehenna Exp $ */
/* $NetBSD: mips_machdep.c,v 1.149 2002/09/09 03:42:04 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -120,7 +120,7 @@
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.148 2002/09/06 13:18:43 gehenna Exp $");
__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.149 2002/09/09 03:42:04 simonb Exp $");
#include "opt_cputype.h"
#include "opt_compat_netbsd.h"
@ -384,19 +384,19 @@ static const struct pridtab cputab[] = {
{ MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0,
MIPS64_FLAGS, "20Kc" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1000, -1, -1, 0,
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1000, -1, -1, 0,
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1500, -1, -1, 0,
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1500 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1500, -1, -1, 0,
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1500 (Rev 2 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1100, -1, -1, 0,
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1100 (Rev 1 core)" },
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1100, -1, -1, 0,
{ MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0,
MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1100 (Rev 2 core)" },
/* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */