From f41231cffc1d55f88633c930ac161661029c3816 Mon Sep 17 00:00:00 2001 From: simonb Date: Mon, 9 Sep 2002 03:42:04 +0000 Subject: [PATCH] Fix the order of the CPU revision and company options fields in the cpu table for the Alchemy CPUs; successfully recognises an Au1500 now. --- sys/arch/mips/mips/mips_machdep.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/sys/arch/mips/mips/mips_machdep.c b/sys/arch/mips/mips/mips_machdep.c index da890699a8c3..076133d635f0 100644 --- a/sys/arch/mips/mips/mips_machdep.c +++ b/sys/arch/mips/mips/mips_machdep.c @@ -1,4 +1,4 @@ -/* $NetBSD: mips_machdep.c,v 1.148 2002/09/06 13:18:43 gehenna Exp $ */ +/* $NetBSD: mips_machdep.c,v 1.149 2002/09/09 03:42:04 simonb Exp $ */ /* * Copyright 2002 Wasabi Systems, Inc. @@ -120,7 +120,7 @@ #include /* RCS ID & Copyright macro defns */ -__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.148 2002/09/06 13:18:43 gehenna Exp $"); +__KERNEL_RCSID(0, "$NetBSD: mips_machdep.c,v 1.149 2002/09/09 03:42:04 simonb Exp $"); #include "opt_cputype.h" #include "opt_compat_netbsd.h" @@ -384,19 +384,19 @@ static const struct pridtab cputab[] = { { MIPS_PRID_CID_MTI, MIPS_20Kc, -1, -1, -1, 0, MIPS64_FLAGS, "20Kc" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1000, -1, -1, 0, + { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1000, -1, 0, MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 1 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1000, -1, -1, 0, + { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1000, -1, 0, MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1000 (Rev 2 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1500, -1, -1, 0, + { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1500, -1, 0, MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1500 (Rev 1 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1500, -1, -1, 0, + { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1500, -1, 0, MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1500 (Rev 2 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, MIPS_AU1100, -1, -1, 0, + { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV1, -1, MIPS_AU1100, -1, 0, MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1100 (Rev 1 core)" }, - { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, MIPS_AU1100, -1, -1, 0, + { MIPS_PRID_CID_ALCHEMY, MIPS_AU_REV2, -1, MIPS_AU1100, -1, 0, MIPS32_FLAGS | CPU_MIPS_NO_WAIT, "Au1100 (Rev 2 core)" }, /* The SB1 CPUs use a CCA of 5 - "Cacheable Coherent Shareable" */