pmap_copy_page, and pmap_clear_modify (pmap_clear_bit). Remove #ifdef
MULTIPROCESSOR since the cache instructions operate on all caches on
all processors.
common across many of the 4xx parts. Leaves ibm405gp.h with device
address information specific to the 405GP CPU. Now allows opb.c to
support multiple 4xx CPU types.
documentation:
- Remove "mainbus" altogether.
- The new root is "plb" - the Processor Local Bus.
- Attached to this is the "opb" - the On-chip Peripheral Bus, to which
all the on-chip devices are attached (except the cpu and pci host
bridge).
- Port-specific code can pass an array of 'struct plb_dev' to
config_rootfound() to attach extra devices to the plb. The walnut
port attaches a "pbus" (Peripheral Bus) in here for the RTC and
pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.
MAC (emac). Much thanks to Jason Thorpe for debugging help writing this
driver. Tested on the walnut, and an earlier version of this driver works
on the OpenBlockSS.
counters. These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.
pmc(9) is meant to be a general interface. Initially, the Intel XScale
counters are the only ones supported.
due to an AST. the rule is that we must always have interrupts
enabled when acquiring kernel_lock, so that we can process blocking IPIs
from another CPU which is already holding kernel_lock.
reduce differences between the MP and non-MP versions of this file.
on the non-boot CPUs, copy the L2CR configuration from the boot CPU.
also, fix the code that configures the L2 cache so that it works at all.
while I'm here, use mfspr() and mtspr() instead of inline asms.
Move call to sched_unlock_idle to later in the context switch to
eliminate a race where another processor could grab the outgoing
process before we were done saving our state into it, with predictable
results.
Bug spotted by Frank van der Linden <fvdl@wasabisystems.com>
also, don't re-enable interrupts temporarily in the middle of
switching to a new process, just wait until we're completely switched.
this didn't work on MP and it's not worth the effort.
data streams on execptions/interrupts since the processor will suspend
them for us. Only stop them on 1) process exit, 2) another process gets
its address space loaded, and 3) (for completeness only) we save a process's
AltiVec context.
remember the "exec"ness of a page. If a managed page is pmap_enter'ed
with VM_PROT_EXECUTE, remember that it's an "exec"page. Such that when
additional mapping are performed, no synch'ing of the I-cache is needed.
Revoke "exec"ness when the page is mapped into the kernel with VM_PROT_WRITE
or the pmap_page_protect is called with VM_PROT_NONE.
reference while relocation is disabled since the stack will be inaccessible.
Add support for using AltiVec in pmap_zero_page and pmap_copy_page on
AltiVec capable processors.
pmap_syncicache. This file uses a ppc feature in a sick and twisted way
to avoid mapping the physical pages used by those routines. It performs
the operations with the MMU disabled but PPC exception save and retstore
the machine state and are invoked with the MMU disabled, this doesn't have
an adverse effect on the system.
Currently only enable for MPC6xx and !OLDPMAP.
Move the trap/vector initialization for MPC6xx ports to mpc6xx_machdep.c
Also move softnet, install_extintr, mapiodev, kvtop. Add common BAT
initialization code.
Add user Altivec support.
Fix calls to OF_call_method in macppc/macppc/machdep.c.
Use ci_fpuproc in cpu_info instead of separate fpuproc.
Add separate syscall.c and defined __HAVE_SYSCALL_INTERN.
* struct sigacts gets a new sigact_sigdesc structure, which has the
sigaction and the trampoline/version. Version 0 means "legacy kernel
provided trampoline". Other versions are coordinated with machine-
dependent code in libc.
* sigaction1() grows two more arguments -- the trampoline pointer and
the trampoline version.
* A new __sigaction_sigtramp() system call is provided to register a
trampoline along with a signal handler.
* The handler is no longer passed to sensig() functions. Instead,
sendsig() looks up the handler by peeking in the sigacts for the
process getting the signal (since it has to look in there for the
trampoline anyway).
* Native sendsig() functions now select the appropriate trampoline and
its arguments based on the trampoline version in the sigacts.
Changes to libc to use the new facility will be checked in later. Kernel
version not bumped; we will ride the 1.6C bump made recently.
16 SR registers when transitioning between kernel and user. Also, don't
reload the kernel SR(s) on every trap but only on traps from user space.
Instead of loading magic SRs for the kernel, load the kernel SRs from the
kernel_pmap_. This makes trap_subr.S completely ignorant of SR uses and
so they can change with having to change trap_subr.S. Also note that
since the user and kernel get complete SR sets, user VA space can now be
increased to 4GB if desired.
Note that we never use a PTE PP of 0 or 1 (supervisor protection) so the
"key" is basically unused. However, use SR_PRKEY for user space is
conceptionally the right thing to do. Currently the kernel_pmap SR(s) are
ignored but that is going to be fixed shortly.
the user's SR registers to the kernel's SR registers on an exception or
interrupt from user level and restored with the user's SR register when the
exception or interrupt returns back to user level.
Makoto Fujiwara <makoto@ki.nu> and Manuel Bouyer <bouyer@netbsd.org>.
Help from Allen Briggs, Jason Thorpe, and Matt Thomas.
We need to call cpu_cache_probe() early in boot (machdep.c).
Add 603 info for completeness, and use NBPG not PAGESIZE, as the
latter relies on uvm being setup (cpu_subr.c).
Let uvm_page_recolor() be called before uvm has been set up; just
note the page coloring value (uvm_page.c).
- implement SIMPLEQ_REMOVE(head, elm, type, field). whilst it's O(n),
this mirrors the functionality of SLIST_REMOVE() (the other
singly-linked list type) and FreeBSD's STAILQ_REMOVE()
- remove the unnecessary elm arg from SIMPLEQ_REMOVE_HEAD().
this mirrors the functionality of SLIST_REMOVE_HEAD() (the other
singly-linked list type) and FreeBSD's STAILQ_REMOVE_HEAD()
- remove notes about SIMPLEQ not supporting arbitrary element removal
- use SIMPLEQ_FOREACH() instead of home-grown for loops
- use SIMPLEQ_EMPTY() appropriately
- use SIMPLEQ_*() instead of accessing sqh_first,sqh_last,sqe_next directly
- reorder manual page; be consistent about how the types are listed
- other minor cleanups
userlevel; this is necessary due to the 601, unlike other 6xx, having
no concept of separated Valid_user vs. Valid_supervisor for BATs.
* When crossing the kernel/userlevel boundary, have platform-provided
hooks set up the two fixed BAT entries, and possibly additional
segment registers to redeem the 601's BAT limitations.
Both of the above are only built if the $MACHINE provides these hooks,
sparing others the pain.
Calculate len separately for icache & dcache in case each has different
cacheline widths. Make the code for both loops the same except for the
dcbst/icbi. Deal with sizes >=2GB properly (like that'll happen but ...)
* Make the extern declaration of the battable array incomplete;
a given port might want to use a differently-sized definition to
support the 601 BAT implementation, where blocks map up to 8M only.
scw