Aren
/
NetBSD
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Clean up some white space niggles.

This commit is contained in:
simonb 2002-07-11 01:38:48 +00:00
parent dd2d708bd5
commit 873edaed34
10 changed files with 122 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
sys/arch/powerpc/ibm4xx/4xx_trap_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: 4xx_trap_subr.S,v 1.1 2001/06/13 06:01:48 simonb Exp $ */
/* $NetBSD: 4xx_trap_subr.S,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -35,7 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
/* This file provides necessary handlers for 405GP CPU
/* This file provides necessary handlers for 405GP CPU
* It should be included in locore.S after powerpc/powerpc/trap_subr.S
*/
@ -57,7 +57,7 @@ _C_LABEL(pitfitwdogsize) = .-_C_LABEL(pitfitwdog)
pithandler:
rfi
ba . /* Protect against prefetch */
wdoghandler:
rfi
ba . /* Protect against prefetch */
@ -66,15 +66,15 @@ wdoghandler:
#define tlbsave 0x3000
#define tlbstack tlbsave+tlbstacksize
/* If an unaligned excception (0x600) and DTLB miss exception (0x1100)
occur at the same time, the interrupt vector offsets of the two
/* If an unaligned excception (0x600) and DTLB miss exception (0x1100)
occur at the same time, the interrupt vector offsets of the two
exceptions are logically OR'ed together to produce 0x1700.
See PPC405GP Rev D/E Errata item 51 */
.globl _C_LABEL(errata51handler),_C_LABEL(errata51size)
_C_LABEL(errata51handler):
ba 0x1100
_C_LABEL(errata51size) = .-_C_LABEL(errata51handler)
_C_LABEL(errata51size) = .-_C_LABEL(errata51handler)
.globl _C_LABEL(tlbdmiss4xx),_C_LABEL(tlbdm4size)
_C_LABEL(tlbdmiss4xx):
@ -83,16 +83,16 @@ _C_LABEL(tlbdmiss4xx):
mfesr r31
stmw r30,16+tlbsave(0)
bla s4xx_miss
_C_LABEL(tlbdm4size) = .-_C_LABEL(tlbdmiss4xx)
_C_LABEL(tlbdm4size) = .-_C_LABEL(tlbdmiss4xx)
.globl _C_LABEL(tlbimiss4xx),_C_LABEL(tlbim4size)
_C_LABEL(tlbimiss4xx):
_C_LABEL(tlbimiss4xx):
STANDARD_PROLOG(tlbsave)
mfsrr0 r30 /* XXX Get fault address */
mfesr r31
stmw r30,16+tlbsave(0)
bla s4xx_miss
_C_LABEL(tlbim4size) = .-_C_LABEL(tlbdmiss4xx)
_C_LABEL(tlbim4size) = .-_C_LABEL(tlbdmiss4xx)
s4xx_miss:
.globl _C_LABEL(pmap_tlbmiss)
@ -106,7 +106,7 @@ s4xx_miss:
mtpid r30
beq 1f
/*
/*
* The kernel we want to switch to is not in the TLB.
* To solve this problem, we will simulate a kernel
* fault on the kernel stack and let the miss handler
@ -121,14 +121,14 @@ s4xx_miss:
lis r1,tlbstack@ha
addi r1,r1,tlbstack@l
stw r30,4(1)
FRAME_SETUP(tlbsave)
/* Take an explicit fault at (kernelstack,pid) */
lwz r3, tlbstack+4(0)
li r4,KERNEL_PID
bl _C_LABEL(pmap_tlbmiss)
/*
/*
* We can retry the old fault or switch stacks and
* take it now. It's easier to retry.
*/
@ -138,7 +138,7 @@ s4xx_miss:
/* kernel stack not in the pmap? we should panic */
trap
ba trapagain
1:
1:
FRAME_SETUP(tlbsave)
lwz r3,FRAME_DEAR+8(1)
lwz r4,FRAME_PID+8(1)
@ -149,10 +149,10 @@ s4xx_miss:
/* XXX DEBUG -- make sure we're not on tlbstack */
addi r7,r1,-tlbsave
twllei r7,(tlbstacksize)
/* PTE not found, time to cause a fault */
/* PTE not found, time to cause a fault */
ba trapagain
2:
2:
FRAME_LEAVE(tlbsave)
rfi
ba . /* Protect against prefetch */

12
sys/arch/powerpc/ibm4xx/clock.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: clock.c,v 1.2 2002/03/15 21:12:07 eeh Exp $ */
/* $NetBSD: clock.c,v 1.3 2002/07/11 01:38:48 simonb Exp $ */
/* $OpenBSD: clock.c,v 1.3 1997/10/13 13:42:53 pefo Exp $ */
/*
@ -64,14 +64,14 @@ static inline u_quad_t mftb(void);
/* Stat clock runs at ~ 95Hz */
#define PERIOD_POWER 21
#define TCR_PERIOD TCR_FP_2_21
#endif
#endif
void
stat_intr(struct clockframe *frame)
{
extern u_long intrcnt[];
mtspr(SPR_TSR, TSR_FIS); /* Clear TSR[FIS] */
intrcnt[CNT_STATCLOCK]++;
statclock(frame);
@ -132,12 +132,12 @@ void
cpu_initclocks(void)
{
ticks_per_intr = ticks_per_sec / hz;
stathz = profhz = ticks_per_sec / (1<<PERIOD_POWER);
stathz = profhz = ticks_per_sec / (1<<PERIOD_POWER);
printf("Setting PIT to %ld/%d = %ld\n", ticks_per_sec, hz, ticks_per_intr);
asm volatile ("mftb %0" : "=r"(lasttb));
mtspr(SPR_PIT, ticks_per_intr);
/* Enable PIT & FIT(2^17c = 0.655ms) interrupts and auto-reload */
mtspr(SPR_TCR, TCR_PIE | TCR_ARE | TCR_FIE | TCR_PERIOD);
mtspr(SPR_TCR, TCR_PIE | TCR_ARE | TCR_FIE | TCR_PERIOD);
}
void
@ -145,7 +145,7 @@ calc_delayconst(void)
{
unsigned int processor_freq;
if (board_info_get("processor-frequency",
if (board_info_get("processor-frequency",
&processor_freq, sizeof(processor_freq)) == -1)
panic("no processor-frequency");

4
sys/arch/powerpc/ibm4xx/copyinstr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: copyinstr.c,v 1.1 2001/06/13 06:01:48 simonb Exp $ */
/* $NetBSD: copyinstr.c,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -81,7 +81,7 @@ copyinstr(const void *udaddr, void *kaddr, size_t len, size_t *done)
"sync; isync;"
"addi %3,%3,1;" /* Inc len */
"or. %2,%2,%2;"
"bdnzf 2,1b;" /*
"bdnzf 2,1b;" /*
* while(ctr-- && !zero)
*/

4
sys/arch/powerpc/ibm4xx/copyoutstr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: copyoutstr.c,v 1.1 2001/06/13 06:01:48 simonb Exp $ */
/* $NetBSD: copyoutstr.c,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -81,7 +81,7 @@ copyoutstr(const void *kaddr, void *udaddr, size_t len, size_t *done)
"sync; isync;"
"addi %3,%3,1;" /* Inc len */
"or. %2,%2,%2;"
"bdnzf 2,1b;" /*
"bdnzf 2,1b;" /*
* while(ctr-- && !zero)
*/

54
sys/arch/powerpc/ibm4xx/cpu.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.c,v 1.2 2002/03/15 21:12:07 eeh Exp $ */
/* $NetBSD: cpu.c,v 1.3 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -90,7 +90,7 @@ cpumatch(struct device *parent, struct cfdata *cf, void *aux)
/* make sure that we're looking for a CPU */
if (strcmp(maa->mb_name, cf->cf_driver->cd_name) != 0)
return (0);
return (0);
return !cpufound;
}
@ -103,7 +103,7 @@ cpuattach(struct device *parent, struct device *self, void *aux)
struct cputab *cp = models;
unsigned int processor_freq;
if (board_info_get("processor-frequency",
if (board_info_get("processor-frequency",
&processor_freq, sizeof(processor_freq)) == -1)
panic("no processor-frequency");
@ -139,9 +139,9 @@ cpuattach(struct device *parent, struct device *self, void *aux)
cpu_probe_cache();
printf("Instruction cache size %d line size %d\n",
printf("Instruction cache size %d line size %d\n",
curcpu()->ci_ci.icache_size, curcpu()->ci_ci.icache_line_size);
printf("Data cache size %d line size %d\n",
printf("Data cache size %d line size %d\n",
curcpu()->ci_ci.dcache_size, curcpu()->ci_ci.dcache_line_size);
#ifdef DEBUG
@ -153,7 +153,7 @@ cpuattach(struct device *parent, struct device *self, void *aux)
/* Initialize ECC error-logging handler. This is always enabled,
* but it will never be called on systems that do not have ECC
* enabled by POST code in the bootloader.
*/
*/
printf("Enabling ecc handler\n");
intr_ecc_tb = 0;
@ -164,8 +164,8 @@ cpuattach(struct device *parent, struct device *self, void *aux)
}
/*
* This routine must be explicitly called to initialize the
* CPU cache information so cache flushe and memcpy operation
* This routine must be explicitly called to initialize the
* CPU cache information so cache flushe and memcpy operation
* work.
*/
void
@ -174,7 +174,7 @@ cpu_probe_cache()
int version;
/*
* First we need to identify the cpu and determine the
* First we need to identify the cpu and determine the
* cache line size, or things like memset/memcpy may lose
* badly.
*/
@ -233,9 +233,9 @@ cpu_probe_cache()
curcpu()->ci_ci.icache_line_size = 32;
break;
default:
/*
* Unknown CPU type. For safety we'll specify a
* cache with a 4-byte line size. That way cache
/*
* Unknown CPU type. For safety we'll specify a
* cache with a 4-byte line size. That way cache
* flush routines won't miss any lines.
*/
curcpu()->ci_ci.dcache_line_size = 4;
@ -318,7 +318,7 @@ intr_ecc(void * arg)
if (board_info_get("mem-size", &memsiz, sizeof(memsiz)) == -1)
panic("no mem-size");
/* This code needs to be improved to handle double-bit errors */
/* in some intelligent fashion. */
@ -328,27 +328,27 @@ intr_ecc(void * arg)
mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_BEAR);
ear = mfdcr(DCR_SDRAM0_CFGDATA);
/* Always clear the error to stop the intr ASAP. */
/* Always clear the error to stop the intr ASAP. */
mtdcr(DCR_SDRAM0_CFGADDR, DCR_SDRAM0_ECCESR);
mtdcr(DCR_SDRAM0_CFGDATA, 0xffffffff);
if (esr == 0x00) {
if (esr == 0x00) {
/* No current error. Could happen due to intr. nesting */
return(1);
};
/* Only report errors every once per second max. Do this using the TB, */
/* because the system time (via microtime) may be adjusted when the date is set */
/* and can't reliably be used to measure intervals. */
asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b"
/* and can't reliably be used to measure intervals. */
asm ("1: mftbu %0; mftb %0+1; mftbu %1; cmpw %0,%1; bne 1b"
: "=r"(tb), "=r"(tmp));
intr_ecc_cnt++;
if ((tb - intr_ecc_tb) < intr_ecc_iv) {
return(1);
};
};
ce = (esr & SDRAM0_ECCESR_CE) != 0x00;
ue = (esr & SDRAM0_ECCESR_UE) != 0x00;
@ -356,14 +356,14 @@ intr_ecc(void * arg)
printf("ECC: Error CNT=%d ESR=%x EAR=%x %s BKNE=%d%d%d%d "
"BLCE=%d%d%d%d CBE=%d%d.\n",
intr_ecc_cnt, esr, ear,
(ue) ? "Uncorrectable" : "Correctable",
((esr & SDRAM0_ECCESR_BKEN(0)) != 0x00),
(ue) ? "Uncorrectable" : "Correctable",
((esr & SDRAM0_ECCESR_BKEN(0)) != 0x00),
((esr & SDRAM0_ECCESR_BKEN(1)) != 0x00),
((esr & SDRAM0_ECCESR_BKEN(2)) != 0x00),
((esr & SDRAM0_ECCESR_BKEN(3)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(0)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(1)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(2)) != 0x00),
((esr & SDRAM0_ECCESR_BKEN(2)) != 0x00),
((esr & SDRAM0_ECCESR_BKEN(3)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(0)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(1)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(2)) != 0x00),
((esr & SDRAM0_ECCESR_BLCEN(3)) != 0x00),
((esr & SDRAM0_ECCESR_CBEN(0)) != 0x00),
((esr & SDRAM0_ECCESR_CBEN(1)) != 0x00));
@ -411,7 +411,7 @@ intr_ecc(void * arg)
/* Should check for uncorrectable errors and panic... */
printf("ECC: Recycling complete, ESR=%x. "
"Checking for persistent errors.\n", esr);
asm volatile(
"mfmsr %0;"
"li %1, 0x00;"

14
sys/arch/powerpc/ibm4xx/intr.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: intr.c,v 1.2 2002/05/13 07:04:24 matt Exp $ */
/* $NetBSD: intr.c,v 1.3 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -103,7 +103,7 @@ ext_intr(void)
pcpl = cpl;
asm volatile ("mfmsr %0" : "=r"(msr));
int_state = mfdcr(DCR_UIC0_MSR); /* Read non-masked interrupt status */
bits_to_clear = int_state;
@ -133,13 +133,13 @@ ext_intr(void)
}
}
mtdcr(DCR_UIC0_SR, bits_to_clear); /* Acknowledge all pending interrupts */
asm volatile ("mtmsr %0" :: "r"(msr | PSL_EE));
splx(pcpl);
asm volatile ("mtmsr %0" :: "r"(msr));
}
static inline void
static inline void
disable_irq(int irq)
{
int mask, omask;
@ -154,7 +154,7 @@ disable_irq(int irq)
#endif
}
static inline void
static inline void
enable_irq(int irq)
{
int mask, omask;
@ -310,7 +310,7 @@ intr_calculatemasks(void)
irqs |= IRQ_TO_MASK(irq);
imask[level] = irqs | SINT_MASK;
}
/*
* IPL_CLOCK should mask clock interrupt even if interrupt handler
* is not registered.
@ -400,7 +400,7 @@ do_pending_int(void)
asm volatile("mtmsr %0" :: "r"(dmsr));
pcpl = cpl; /* Turn off all */
again:
again:
while ((hwpend = ipending & ~pcpl & HWINT_MASK)) {
irq = cntlzw(hwpend);
enable_irq(irq);

4
sys/arch/powerpc/ibm4xx/mainbus.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: mainbus.c,v 1.1 2002/03/13 01:04:16 eeh Exp $ */
/* $NetBSD: mainbus.c,v 1.2 2002/07/11 01:38:48 simonb Exp $ */
/*
* Copyright 2002 Wasabi Systems, Inc.
@ -126,7 +126,7 @@ mainbus_attach(struct device *parent, struct device *self, void *aux)
mba.mba_bt = sc->bt;
mba.mba_dmat = sc->dmat;
config_found(self, &mba, mainbus_print);
/* Attach all other devices. */
config_search(mainbus_search, self, NULL);
}

37
sys/arch/powerpc/ibm4xx/pmap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: pmap.c,v 1.11 2002/03/28 18:07:31 eeh Exp $ */
/* $NetBSD: pmap.c,v 1.12 2002/07/11 01:38:49 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -484,7 +484,7 @@ pmap_virtual_space(vaddr_t *start, vaddr_t *end)
/*
* Preallocate kernel page tables to a specified VA.
* This simply loops through the first TTE for each
* page table from the beginning of the kernel pmap,
* page table from the beginning of the kernel pmap,
* reads the entry, and if the result is
* zero (either invalid entry or no page table) it stores
* a zero there, populating page tables in the process.
@ -496,15 +496,15 @@ extern void vm_page_free1 __P((struct vm_page *));
vaddr_t kbreak = VM_MIN_KERNEL_ADDRESS;
vaddr_t
vaddr_t
pmap_growkernel(maxkvaddr)
vaddr_t maxkvaddr;
vaddr_t maxkvaddr;
{
int s;
int seg;
paddr_t pg;
struct pmap *pm = pmap_kernel();
s = splvm();
/* Align with the start of a page table */
@ -513,7 +513,7 @@ pmap_growkernel(maxkvaddr)
seg = STIDX(kbreak);
if (pte_find(pm, kbreak)) continue;
if (uvm.page_init_done) {
pg = (paddr_t)VM_PAGE_TO_PHYS(vm_page_alloc1());
} else {
@ -897,9 +897,9 @@ pmap_unwire(struct pmap *pm, vaddr_t va)
paddr_t pa;
int s = splvm();
if (pm == NULL) {
return;
}
if (pm == NULL) {
return;
}
if (!pmap_extract(pm, va, &pa)) {
return;
@ -1183,7 +1183,7 @@ pmap_procwr(struct proc *p, vaddr_t va, size_t len)
"mfpid %1;"
"mtpid %2;"
"sync; isync;"
"1:"
"1:"
"dcbf 0,%3;"
"icbi 0,%3;"
"addi %3,%3,32;"
@ -1268,7 +1268,7 @@ ppc4xx_tlb_find_victim(void)
if (++tlbnext >= NTLB)
tlbnext = TLB_NRESERVED;
flags = tlb_info[tlbnext].ti_flags;
if (!(flags & TLBF_USED) ||
if (!(flags & TLBF_USED) ||
(flags & (TLBF_LOCKED | TLBF_REF)) == 0) {
u_long va, stack = (u_long)&va;
@ -1297,7 +1297,6 @@ ppc4xx_tlb_enter(int ctx, vaddr_t va, u_int pte)
paddr_t pa;
int s, sz;
tlbenter_ev.ev_count++;
sz = (pte & TTE_SZ_MASK) >> TTE_SZ_SHIFT;
@ -1314,7 +1313,7 @@ ppc4xx_tlb_enter(int ctx, vaddr_t va, u_int pte)
panic("ppc4xx_tlb_enter: repacing entry %ld\n", idx);
}
#endif
tlb_info[idx].ti_va = (va & TLB_EPN_MASK);
tlb_info[idx].ti_ctx = ctx;
tlb_info[idx].ti_flags = TLBF_USED | TLBF_REF;
@ -1584,7 +1583,7 @@ pmap_testout()
printf("Clearing page va %p pa %lx: ref %d, mod %d\n",
(void *)(u_long)va, (long)pa,
ref, mod);
/* Modify page */
*loc = 1;
@ -1643,7 +1642,7 @@ pmap_testout()
printf("Clearing page va %p pa %lx: ref %d, mod %d\n",
(void *)(u_long)va, (long)pa,
ref, mod);
/* Modify page */
#if 0
pmap_enter(pmap_kernel(), va, pa, VM_PROT_ALL, 0);
@ -1685,7 +1684,7 @@ pmap_testout()
printf("Clearing page va %p pa %lx: ref %d, mod %d\n",
(void *)(u_long)va, (long)pa,
ref, mod);
/* Modify page */
#if 0
pmap_enter(pmap_kernel(), va, pa, VM_PROT_ALL, 0);
@ -1726,7 +1725,7 @@ pmap_testout()
printf("Clearing page va %p pa %lx: ref %d, mod %d\n",
(void *)(u_long)va, (long)pa,
ref, mod);
/* Modify page */
#if 0
pmap_enter(pmap_kernel(), va, pa, VM_PROT_ALL, 0);
@ -1768,7 +1767,7 @@ pmap_testout()
printf("Clearing page va %p pa %lx: ref %d, mod %d\n",
(void *)(u_long)va, (long)pa,
ref, mod);
/* Modify page */
#if 0
pmap_enter(pmap_kernel(), va, pa, VM_PROT_ALL, 0);
@ -1800,7 +1799,7 @@ pmap_testout()
printf("Checking cleared page: ref %d, mod %d\n",
ref, mod);
pmap_enter(pmap_kernel(), va, pa, VM_PROT_ALL,
pmap_enter(pmap_kernel(), va, pa, VM_PROT_ALL,
VM_PROT_ALL|PMAP_WIRED);
uvm_km_free(kernel_map, (vaddr_t)va, NBPG);
}

36
sys/arch/powerpc/ibm4xx/trap.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap.c,v 1.6 2002/07/05 18:45:20 matt Exp $ */
/* $NetBSD: trap.c,v 1.7 2002/07/11 01:38:49 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -143,7 +143,7 @@ trap(struct trapframe *frame)
ftype = VM_PROT_READ;
DBPRINTF(TDB_ALL, ("trap(%x) at %x from frame %p &frame %p\n",
DBPRINTF(TDB_ALL, ("trap(%x) at %x from frame %p &frame %p\n",
type, frame->srr0, frame, &frame));
switch (type) {
@ -162,9 +162,9 @@ printf("debug reg is %x srr2 %x srr3 %x\n", rv, srr2, srr3);
trapsignal(p, SIGTRAP, EXC_TRC);
KERNEL_PROC_UNLOCK(p);
break;
/* If we could not find and install appropriate TLB entry, fall through */
case EXC_DSI:
/* FALLTHROUGH */
case EXC_DTMISS:
@ -184,7 +184,7 @@ printf("debug reg is %x srr2 %x srr3 %x\n", rv, srr2, srr3);
if (frame->esr & (ESR_DST|ESR_DIZ))
ftype = VM_PROT_WRITE;
DBPRINTF(TDB_ALL, ("trap(EXC_DSI) at %x %s fault on %p esr %x\n",
DBPRINTF(TDB_ALL, ("trap(EXC_DSI) at %x %s fault on %p esr %x\n",
frame->srr0, (ftype&VM_PROT_WRITE) ? "write" : "read", (void *)va, frame->esr));
rv = uvm_fault(map, trunc_page(va), 0, ftype);
KERNEL_UNLOCK();
@ -204,16 +204,16 @@ frame->srr0, (ftype&VM_PROT_WRITE) ? "write" : "read", (void *)va, frame->esr));
}
}
goto brain_damage;
case EXC_DSI|EXC_USER:
/* FALLTHROUGH */
case EXC_DTMISS|EXC_USER:
KERNEL_PROC_LOCK(p);
if (frame->esr & (ESR_DST|ESR_DIZ))
ftype = VM_PROT_WRITE;
DBPRINTF(TDB_ALL, ("trap(EXC_DSI|EXC_USER) at %x %s fault on %x %x\n",
DBPRINTF(TDB_ALL, ("trap(EXC_DSI|EXC_USER) at %x %s fault on %x %x\n",
frame->srr0, (ftype&VM_PROT_WRITE) ? "write" : "read", frame->dear, frame->esr));
KASSERT(p == curproc && (p->p_stat == SONPROC));
rv = uvm_fault(&p->p_vmspace->vm_map,
@ -238,7 +238,7 @@ KASSERT(p == curproc && (p->p_stat == SONPROC));
case EXC_ISI|EXC_USER:
KERNEL_PROC_LOCK(p);
ftype = VM_PROT_READ | VM_PROT_EXECUTE;
DBPRINTF(TDB_ALL, ("trap(EXC_ISI|EXC_USER) at %x %s fault on %x tf %p\n",
DBPRINTF(TDB_ALL, ("trap(EXC_ISI|EXC_USER) at %x %s fault on %x tf %p\n",
frame->srr0, (ftype&VM_PROT_WRITE) ? "write" : "read", frame->srr0, frame));
rv = uvm_fault(&p->p_vmspace->vm_map, trunc_page(frame->srr0), 0, ftype);
if (rv == 0) {
@ -278,10 +278,10 @@ frame->srr0, (ftype&VM_PROT_WRITE) ? "write" : "read", frame->srr0, frame));
break;
case EXC_PGM|EXC_USER:
/*
* Illegal insn:
/*
* Illegal insn:
*
* let's try to see if it's FPU and can be emulated.
* let's try to see if it's FPU and can be emulated.
*/
uvmexp.traps ++;
if (!(p->p_addr->u_pcb.pcb_flags & PCB_FPU)) {
@ -290,7 +290,7 @@ frame->srr0, (ftype&VM_PROT_WRITE) ? "write" : "read", frame->srr0, frame));
p->p_addr->u_pcb.pcb_flags |= PCB_FPU;
}
if ((rv = fpu_emulate(frame,
if ((rv = fpu_emulate(frame,
(struct fpreg *)&p->p_addr->u_pcb.pcb_fpu))) {
KERNEL_PROC_LOCK(p);
trapsignal(p, rv, EXC_PGM);
@ -442,7 +442,7 @@ bigcopyin(const void *udaddr, void *kaddr, size_t len)
}
/*
* Stolen from physio():
* Stolen from physio():
*/
PHOLD(p);
error = uvm_vslock(p, (caddr_t)udaddr, len, VM_PROT_READ);
@ -457,7 +457,7 @@ bigcopyin(const void *udaddr, void *kaddr, size_t len)
uvm_vsunlock(p, (caddr_t)udaddr, len);
PRELE(p);
return 0;
return 0;
}
int
@ -519,7 +519,7 @@ bigcopyout(const void *kaddr, void *udaddr, size_t len)
}
/*
* Stolen from physio():
* Stolen from physio():
*/
PHOLD(p);
error = uvm_vslock(p, udaddr, len, VM_PROT_WRITE);
@ -527,7 +527,7 @@ bigcopyout(const void *kaddr, void *udaddr, size_t len)
PRELE(p);
return EFAULT;
}
up = (char *)vmaprange(p, (vaddr_t)udaddr, len,
up = (char *)vmaprange(p, (vaddr_t)udaddr, len,
VM_PROT_READ|VM_PROT_WRITE);
memcpy(up, kp, len);
@ -535,7 +535,7 @@ bigcopyout(const void *kaddr, void *udaddr, size_t len)
uvm_vsunlock(p, udaddr, len);
PRELE(p);
return 0;
return 0;
}
/*

46
sys/arch/powerpc/ibm4xx/trap_subr.S
View File

@ -1,4 +1,4 @@
/* $NetBSD: trap_subr.S,v 1.3 2002/03/13 19:11:53 eeh Exp $ */
/* $NetBSD: trap_subr.S,v 1.4 2002/07/11 01:38:49 simonb Exp $ */
/*
* Copyright 2001 Wasabi Systems, Inc.
@ -93,7 +93,7 @@ GLOBAL(intr_depth)
.comm spillstk,SPILLSTK,8
#if defined(MULTIPROCESSOR)
#define GET_PCB(rX) \
#define GET_PCB(rX) \
GET_CPUINFO(rX); \
lwz rX,CI_CURPCB(rX)
#else
@ -113,7 +113,7 @@ GLOBAL(intr_depth)
GET_PCB(1); \
addi 1,1,USPACE; /* stack is top of user struct */ \
1:
#define CRITICAL_PROLOG(savearea) \
mtsprg 1,1; /* save SP */ \
stmw 28,savearea(0); /* free r28-r31 */ \
@ -130,7 +130,7 @@ GLOBAL(intr_depth)
1:
/* Standard handler saves r1,r28-31,LR,CR, sets up the stack and calls s_trap */
/* Standard handler saves r1,r28-31,LR,CR, sets up the stack and calls s_trap */
#define STANDARD_EXC_HANDLER(name)\
.globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
_C_LABEL(name ## trap): \
@ -138,7 +138,7 @@ _C_LABEL(name ## trap): \
bla s_trap ; \
_C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
/* Access exceptions also need DEAR and ESR saved */
/* Access exceptions also need DEAR and ESR saved */
#define ACCESS_EXC_HANDLER(name)\
.globl _C_LABEL(name ## trap),_C_LABEL(name ## size) ; \
_C_LABEL(name ## trap): \
@ -156,10 +156,10 @@ _C_LABEL(name ## trap): \
CRITICAL_PROLOG(tempsave); \
bla s_trap ; \
_C_LABEL(name ## size) = .-_C_LABEL(name ## trap)
/*
* This code gets copied to all the trap vectors
* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
* (except ISI/DSI, ALI, the interrupts, and possibly the debugging
* traps when using IPKDB).
*/
.text
@ -191,7 +191,7 @@ _C_LABEL(extint):
ba extintr
_C_LABEL(extsize) = .-_C_LABEL(extint)
#ifdef DDB
#define ddbsave 0xde0 /* primary save area for DDB */
/*
@ -238,7 +238,7 @@ _C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
#else
#define TRAP_IF_ZERO(r)
#endif
/*
* FRAME_SETUP assumes:
* SPRG1 SP (1)
@ -315,14 +315,14 @@ _C_LABEL(ipkdbsize) = .-_C_LABEL(ipkdblow)
realtrap: /* entry point after IPKDB is done with exception */
/* Test whether we already had PR set */
mfsrr1 1
mtcr 1
mfsprg 1,1 /* restore SP (might have been
overwritten) */
bc 4,17,s_trap /* branch if PSL_PR is false */
lis 1,_C_LABEL(curpcb)@ha
lwz 1,_C_LABEL(curpcb)@l(1)
addi 1,1,USPACE /* stack is top of user struct */
mfsrr1 1
mtcr 1
mfsprg 1,1 /* restore SP (might have been
overwritten) */
bc 4,17,s_trap /* branch if PSL_PR is false */
lis 1,_C_LABEL(curpcb)@ha
lwz 1,_C_LABEL(curpcb)@l(1)
addi 1,1,USPACE /* stack is top of user struct */
/*
* Now the common trap catching code.
*/
@ -361,7 +361,7 @@ _C_LABEL(trapexit):
/*
* External interrupt second level handler
*/
#define INTRENTER \
/* Save non-volatile registers: */ \
stwu 1,-92(1); /* temporarily */ \
@ -421,7 +421,7 @@ intr_exit:
mtmsr 5
isync
mtpid 3 /* Load CTX */
/* restore possibly overwritten registers: */
lwz 12,44(1)
lwz 11,48(1)
@ -485,7 +485,7 @@ intr_exit:
lwz 1,0(1)
rfi
ba . /* Protect against prefetch */
/*
* PIT interrupt handler.
*/
@ -647,7 +647,7 @@ _C_LABEL(ipkdbfbyte):
lwz 8,_C_LABEL(ipkdbsr)@l(8)
mtsr USER_SR,8
isync
#endif
#endif
#endif
dcbst 0,9 /* flush data... */
sync
@ -675,7 +675,7 @@ _C_LABEL(ipkdbsbyte):
lwz 8,_C_LABEL(ipkdbsr)@l(8)
mtsr USER_SR,8
isync
#endif
#endif
#endif
dcbst 0,9 /* flush data... */
sync
@ -690,6 +690,6 @@ _C_LABEL(ipkdbsbyte):
stw 5,0(9) /* restore previous fault handler */
dcbst 0,9 /* and flush data... */
sync
icbi 0,9 /* and instruction caches */
icbi 0,9 /* and instruction caches */
blr
#endif /* IPKDB */