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Add a bunch of mpc8xx SPR definitions.

This commit is contained in:
matt 2002-08-14 15:38:40 +00:00
parent f4091be169
commit 571dd402e2
1 changed files with 119 additions and 32 deletions
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151
sys/arch/powerpc/include/spr.h
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@ -1,4 +1,4 @@
/* $NetBSD: spr.h,v 1.24 2002/08/11 13:33:00 simonb Exp $ */
/* $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ */
#ifndef _POWERPC_SPR_H_
#define _POWERPC_SPR_H_
@ -42,6 +42,9 @@
#define SPR_SDR1 0x019 /* .68 Page table base address register */
#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */
#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */
#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */
#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */
#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */
#define SPR_SPRG0 0x110 /* 468 SPR General 0 */
@ -87,37 +90,121 @@
#define MPC8245 0x8081
#define SPR_IBAT0U 0x210 /* .68 Instruction BAT Reg 0 Upper */
#define SPR_IBAT0L 0x211 /* .68 Instruction BAT Reg 0 Lower */
#define SPR_IBAT1U 0x212 /* .68 Instruction BAT Reg 1 Upper */
#define SPR_IBAT1L 0x213 /* .68 Instruction BAT Reg 1 Lower */
#define SPR_IBAT2U 0x214 /* .68 Instruction BAT Reg 2 Upper */
#define SPR_IBAT2L 0x215 /* .68 Instruction BAT Reg 2 Lower */
#define SPR_IBAT3U 0x216 /* .68 Instruction BAT Reg 3 Upper */
#define SPR_IBAT3L 0x217 /* .68 Instruction BAT Reg 3 Lower */
#define SPR_DBAT0U 0x218 /* .68 Data BAT Reg 0 Upper */
#define SPR_DBAT0L 0x219 /* .68 Data BAT Reg 0 Lower */
#define SPR_DBAT1U 0x21a /* .68 Data BAT Reg 1 Upper */
#define SPR_DBAT1L 0x21b /* .68 Data BAT Reg 1 Lower */
#define SPR_DBAT2U 0x21c /* .68 Data BAT Reg 2 Upper */
#define SPR_DBAT2L 0x21d /* .68 Data BAT Reg 2 Lower */
#define SPR_DBAT3U 0x21e /* .68 Data BAT Reg 3 Upper */
#define SPR_DBAT3L 0x21f /* .68 Data BAT Reg 3 Lower */
#define SPI_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
#define SPI_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
#define SPI_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
#define SPI_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
#define SPI_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
#define SPI_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
#define SPI_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
#define SPI_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
#define SPI_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
#define SPI_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
#define SPI_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
#define SPI_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
#define SPI_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
#define SPI_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
#define SPI_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
#define SPI_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */
#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */
#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */
#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */
#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */
#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */
#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */
#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */
#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */
#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */
#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */
#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */
#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */
#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */
#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */
#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */
#define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */
#define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */
#define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */
#define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */
#define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */
#define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */
#define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */
#define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */
#define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */
#define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */
#define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */
#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */
#define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */
#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */
#define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */
#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */
#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */
#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */
#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */
#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */
#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */
#define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */
#define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */
#define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */
#define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */
#define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */
#define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */
#define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */
#define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */
#define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */
#define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */
#define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */
#define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */
#define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */
#define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */
#define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */
#define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */
#define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */
#define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */
#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */
#define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */
#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */
#define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */
#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */
#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */
#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */
#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */
#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */
#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */
#define SPR_MI_CTR 0x310 /* ..8 IMMU control */
#define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */
#define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */
#define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */
#define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */
#define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */
#define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */
#define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */
#define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */
#define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */
#define SPR_MI_AP 0x312 /* ..8 IMMU access protection */
#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */
#define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */
#define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */
#define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */
#define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */
#define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */
#define Mx_EPN_EV 0x00000020 /* Entry Valid */
#define Mx_EPN_ASID 0x0000000f /* Address Space ID */
#define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */
#define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */
#define Mx_TWC_APG 0x000001e0 /* Access Protection Group */
#define Mx_TWC_G 0x00000010 /* Guarded memory */
#define Mx_TWC_PS 0x0000000c /* Page Size (L1) */
#define MD_TWC_WT 0x00000002 /* Write-Through */
#define Mx_TWC_V 0x00000001 /* Entry Valid */
#define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */
#define Mx_RPN_RPN 0xfffff000 /* Real Page Number */
#define Mx_RPN_PP 0x00000ff0 /* Page Protection */
#define Mx_RPN_SPS 0x00000008 /* Small Page Size */
#define Mx_RPN_SH 0x00000004 /* SHared page */
#define Mx_RPN_CI 0x00000002 /* Cache Inhibit */
#define Mx_RPN_V 0x00000001 /* Valid */
#define SPR_MD_CTR 0x318 /* ..8 DMMU control */
#define SPR_M_CASID 0x319 /* ..8 CASID */
#define M_CASID 0x0000000f /* Current AS Id */
#define SPR_MD_AP 0x31a /* ..8 DMMU access protection */
#define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */
#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */
#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
#define M_TWB_L1INDX 0x00000ffc /* level-1 index */
#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */
#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */
#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */
#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */
#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */
#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */
#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */
#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */
#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */
#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */
#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */
#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */