on MP systems, if the firmware didn't configure the L2 cache
on the non-boot CPUs, copy the L2CR configuration from the boot CPU. also, fix the code that configures the L2 cache so that it works at all. while I'm here, use mfspr() and mtspr() instead of inline asms.
This commit is contained in:
chs
parent
2928d8ba05
commit
f73abf90fb
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@ -1,4 +1,4 @@
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/* $NetBSD: cpu_subr.c,v 1.25 2002/07/28 07:03:15 chs Exp $ */
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/* $NetBSD: cpu_subr.c,v 1.26 2002/08/06 06:20:08 chs Exp $ */
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/*-
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* Copyright (c) 2001 Matt Thomas.
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@ -43,6 +43,7 @@
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <powerpc/mpc6xx/hid.h>
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#include <powerpc/mpc6xx/hid_601.h>
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#include <powerpc/spr.h>
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@ -76,7 +77,7 @@ cpu_probe_cache(void)
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{
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u_int assoc, pvr, vers;
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__asm __volatile ("mfpvr %0" : "=r"(pvr));
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pvr = mfpvr();
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vers = pvr >> 16;
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switch (vers) {
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@ -154,7 +155,7 @@ cpu_attach_common(struct device *self, int id)
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ci->ci_intrdepth = -1;
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ci->ci_dev = self;
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__asm __volatile ("mfpvr %0" : "=r"(pvr));
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pvr = mfpvr();
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vers = (pvr >> 16) & 0xffff;
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switch (id) {
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@ -168,7 +169,7 @@ cpu_attach_common(struct device *self, int id)
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case MPC7410:
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case MPC7450:
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case MPC7455:
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__asm __volatile ("mtspr %1,%0" :: "r"(id), "n"(SPR_PIR));
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mtspr(SPR_PIR, id);
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}
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cpu_setup(self, ci);
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break;
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@ -191,16 +192,17 @@ cpu_setup(self, ci)
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struct cpu_info *ci;
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{
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u_int hid0, pvr, vers;
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char *bitmask, hidbuf[128];
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char model[80];
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__asm __volatile ("mfpvr %0" : "=r"(pvr));
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pvr = mfpvr();
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vers = (pvr >> 16) & 0xffff;
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cpu_identify(model, sizeof(model));
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printf(": %s, ID %d%s\n", model, cpu_number(),
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cpu_number() == 0 ? " (primary)" : "");
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__asm __volatile("mfspr %0,%1" : "=r"(hid0) : "n"(SPR_HID0));
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hid0 = mfspr(SPR_HID0);
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cpu_probe_cache();
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/*
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@ -256,38 +258,31 @@ cpu_setup(self, ci)
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hid0 &= ~HID0_DBP; /* XXX correct? */
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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break;
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#if 0
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case MPC7400:
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case MPC7410:
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hid0 &= ~HID0_SPD;
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hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT;
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hid0 |= HID0_EIEC;
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break;
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#endif
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}
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__asm __volatile ("mtspr %1,%0" :: "r"(hid0), "n"(SPR_HID0));
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mtspr(SPR_HID0, hid0);
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#if 1
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{
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char hidbuf[128];
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char *bitmask;
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switch (vers) {
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case MPC601:
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bitmask = HID0_601_BITMASK;
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break;
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case MPC7450:
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case MPC7455:
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bitmask = HID0_7450_BITMASK;
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break;
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default:
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bitmask = HID0_BITMASK;
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break;
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}
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bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf);
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printf("%s: HID0 %s\n", self->dv_xname, hidbuf);
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switch (vers) {
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case MPC601:
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bitmask = HID0_601_BITMASK;
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break;
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case MPC7450:
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case MPC7455:
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bitmask = HID0_7450_BITMASK;
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break;
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default:
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bitmask = HID0_BITMASK;
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break;
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}
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#endif
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bitmask_snprintf(hid0, bitmask, hidbuf, sizeof hidbuf);
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printf("%s: HID0 %s\n", self->dv_xname, hidbuf);
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/*
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* Display speed and cache configuration.
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@ -377,7 +372,7 @@ cpu_identify(char *str, size_t len)
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u_int pvr, vers, maj, min;
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const struct cputab *cp;
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asm ("mfpvr %0" : "=r"(pvr));
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pvr = mfpvr();
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vers = pvr >> 16;
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switch (vers) {
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case MPC7410:
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@ -403,7 +398,8 @@ cpu_identify(char *str, size_t len)
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if (cp->name != NULL) {
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snprintf(str, len, "%s (Revision %u.%u)", cp->name, maj, min);
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} else {
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snprintf(str, len, "Version %x (Revision %u.%u)", vers, maj, min);
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snprintf(str, len, "Version %x (Revision %u.%u)", vers, maj,
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min);
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}
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}
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@ -416,31 +412,48 @@ u_int l2cr_config = 0;
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void
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cpu_config_l2cr(int vers)
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{
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u_int l2cr, x;
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u_int l2cr, x, msr;
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__asm __volatile ("mfspr %0,%1" : "=r"(l2cr) : "n"(SPR_L2CR));
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l2cr = mfspr(SPR_L2CR);
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/*
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* For MP systems, the firmware may only configure the L2 cache
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* on the first CPU. In this case, assume that the other CPUs
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* should use the same value for L2CR.
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*/
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if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) {
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l2cr_config = l2cr;
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}
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/*
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* Configure L2 cache if not enabled.
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*/
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if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) {
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l2cr = l2cr_config;
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asm volatile ("mtspr %1,%0" :: "r"(l2cr), "n"(SPR_L2CR));
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/* Disable interrupts and set the cache config bits. */
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msr = mfmsr();
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mtmsr(msr & ~PSL_EE);
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#ifdef ALTIVEC
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asm volatile("dssall");
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#endif
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asm volatile("sync");
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mtspr(SPR_L2CR, l2cr & ~L2CR_L2E);
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asm volatile("sync");
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/* Wait for L2 clock to be stable (640 L2 clocks). */
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delay(100);
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/* Invalidate all L2 contents. */
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l2cr |= L2CR_L2I;
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asm volatile ("mtspr %1,%0" :: "r"(l2cr), "n"(SPR_L2CR));
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mtspr(SPR_L2CR, l2cr | L2CR_L2I);
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do {
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asm volatile ("mfspr %0,%1" : "=r"(x) : "n"(SPR_L2CR));
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x = mfspr(SPR_L2CR);
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} while (x & L2CR_L2IP);
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/* Enable L2 cache. */
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l2cr &= ~L2CR_L2I;
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l2cr |= L2CR_L2E;
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asm volatile ("mtspr %1,%0" :: "r"(l2cr), "n"(SPR_L2CR));
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mtspr(SPR_L2CR, l2cr);
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mtmsr(msr);
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}
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if (l2cr & L2CR_L2E) {
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@ -449,8 +462,7 @@ cpu_config_l2cr(int vers)
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printf(": 256KB L2 cache");
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__asm __volatile("mfspr %0,%1" :
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"=r"(l3cr) : "n"(SPR_L3CR) );
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l3cr = mfspr(SPR_L3CR);
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if (l3cr & L3CR_L3E)
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printf(", %cMB L3 backside cache",
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l3cr & L3CR_L3SIZ ? '2' : '1');
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@ -474,7 +486,11 @@ cpu_config_l2cr(int vers)
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default:
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printf(": unknown size");
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}
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#if 0
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if (l2cr & L2CR_L2WT) {
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printf(" write-through");
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} else {
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printf(" write-back");
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}
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switch (l2cr & L2CR_L2RAM) {
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case L2RAM_FLOWTHRU_BURST:
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printf(" Flow-through synchronous burst SRAM");
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@ -491,7 +507,6 @@ cpu_config_l2cr(int vers)
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if (l2cr & L2CR_L2PE)
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printf(" with parity");
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#endif
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printf(" backside cache");
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} else
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printf(": L2 cache not enabled");
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@ -502,7 +517,7 @@ cpu_config_l2cr(int vers)
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void
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cpu_print_speed(void)
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{
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u_int64_t cps;
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uint64_t cps;
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mtspr(SPR_MMCR0, SPR_MMCR0_FC);
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mtspr(SPR_PMC1, 0);
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delay(100000);
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cps = (mfspr(SPR_PMC1) * 10) + 4999;
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printf(": %qd.%02qd MHz\n", cps / 1000000, (cps / 10000) % 100);
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printf(": %lld.%02lld MHz\n", cps / 1000000, (cps / 10000) % 100);
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}
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#if NSYSMON_ENVSYS > 0
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