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Use size_t in prototype (so this will be LP64 clean for PPC64 someday). 

Calculate len separately for icache & dcache in case each has different
cacheline widths.  Make the code for both loops the same except for the
dcbst/icbi.  Deal with sizes >=2GB properly (like that'll happen but ...)
This commit is contained in:
matt 2002-03-26 21:20:24 +00:00
parent dde8f75509
commit 12810ed37d
3 changed files with 22 additions and 20 deletions
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19
lib/libc/arch/powerpc/gen/syncicache.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: syncicache.c,v 1.8 2002/03/18 05:10:58 dbj Exp $ */
/* $NetBSD: syncicache.c,v 1.9 2002/03/26 21:20:24 matt Exp $ */
/*
* Copyright (C) 1995-1997, 1999 Wolfgang Solfrank.
@ -92,11 +92,11 @@ getcachelinesize(void)
#endif
void
__syncicache(void *from, int len)
__syncicache(void *from, size_t len)
{
int l, off;
size_t l, off;
size_t linesz;
char *p;
int linesz;
#if !defined(_KERNEL) && !defined(_STANDALONE)
if (!_cachelinesize)
@ -105,24 +105,25 @@ __syncicache(void *from, int len)
if (CACHEINFO.dcache_size > 0) {
linesz = CACHEINFO.dcache_line_size;
off = (u_int)from & (linesz - 1);
l = len += off;
off = (uintptr_t)from & (linesz - 1);
l = (len + off + linesz - 1) & ~(linesz - 1);
p = (char *)from - off;
do {
__asm__ __volatile ("dcbst 0,%0" :: "r"(p));
p += linesz;
} while ((l -= linesz) > 0);
} while ((l -= linesz) != 0);
}
__asm__ __volatile ("sync");
if (CACHEINFO.icache_size > 0 ) {
linesz = CACHEINFO.icache_line_size;
off = (u_int)from & (linesz - 1);
off = (uintptr_t)from & (linesz - 1);
l = (len + off + linesz - 1) & ~(linesz - 1);
p = (char *)from - off;
do {
__asm__ __volatile ("icbi 0,%0" :: "r"(p));
p += linesz;
} while ((len -= linesz) > 0);
} while ((l -= linesz) != 0);
}
__asm__ __volatile ("isync");
}

4
sys/arch/powerpc/include/cpu.h
View File

@ -1,4 +1,4 @@
/* $NetBSD: cpu.h,v 1.14 2002/03/13 00:38:13 eeh Exp $ */
/* $NetBSD: cpu.h,v 1.15 2002/03/26 21:20:24 matt Exp $ */
/*
* Copyright (C) 1999 Wolfgang Solfrank.
@ -184,7 +184,7 @@ extern void icache_flush(vaddr_t, vsize_t);
#endif
#endif
void __syncicache(void *, int);
void __syncicache(void *, size_t);
/*

19
sys/lib/libkern/arch/powerpc/syncicache.c
View File

@ -1,4 +1,4 @@
/* $NetBSD: syncicache.c,v 1.6 2002/03/18 05:10:59 dbj Exp $ */
/* $NetBSD: syncicache.c,v 1.7 2002/03/26 21:20:24 matt Exp $ */
/*
* Copyright (C) 1995-1997, 1999 Wolfgang Solfrank.
@ -92,11 +92,11 @@ getcachelinesize(void)
#endif
void
__syncicache(void *from, int len)
__syncicache(void *from, size_t len)
{
int l, off;
size_t l, off;
size_t linesz;
char *p;
int linesz;
#if !defined(_KERNEL) && !defined(_STANDALONE)
if (!_cachelinesize)
@ -105,24 +105,25 @@ __syncicache(void *from, int len)
if (CACHEINFO.dcache_size > 0) {
linesz = CACHEINFO.dcache_line_size;
off = (u_int)from & (linesz - 1);
l = len += off;
off = (uintptr_t)from & (linesz - 1);
l = (len + off + linesz - 1) & ~(linesz - 1);
p = (char *)from - off;
do {
__asm__ __volatile ("dcbst 0,%0" :: "r"(p));
p += linesz;
} while ((l -= linesz) > 0);
} while ((l -= linesz) != 0);
}
__asm__ __volatile ("sync");
if (CACHEINFO.icache_size > 0 ) {
linesz = CACHEINFO.icache_line_size;
off = (u_int)from & (linesz - 1);
off = (uintptr_t)from & (linesz - 1);
l = (len + off + linesz - 1) & ~(linesz - 1);
p = (char *)from - off;
do {
__asm__ __volatile ("icbi 0,%0" :: "r"(p));
p += linesz;
} while ((len -= linesz) > 0);
} while ((l -= linesz) != 0);
}
__asm__ __volatile ("isync");
}