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859 Commits

Author SHA1 Message Date
jeffs
ef9531850e Add comment that overriding the sysctl defines in machine/cpu.h 
breaks userland binary compatiabiltiy between mips ports.  Move
check down so common values are always defined here.
 2000-07-13 07:37:11 +00:00
jeffs
f6812b853b Only define machdep sysctls if CPU_MAXID is not defined by machine/cpu.h. 
This lets mips ports have additional machdep sysctl.  Define CPUISMIPS3
for MIPS1+MIPS2 as cpu_arch >= 3 to support mips4.  Add cpu_intr()
prototype so this is defined in one place.
 2000-07-11 06:34:57 +00:00
jeffs
6b28794054 Add support for 3 QED special2 opcodes. 2000-07-11 06:27:58 +00:00
jeffs
54a85cb3af For 64b clean 32b compilation, do not bother setting SX And KX. 
The current code does not maintain these in SR, and they are not
needed by 32b kernel code for mips3/4 instructions.
 2000-07-11 06:26:08 +00:00
soren
77e30d85bf Oops. 2000-07-11 01:15:47 +00:00
jeffs
dcbf69bf94 Update mips3_locore_vec cache functions for mips3_L1TwoWayCache. Add cast 
for clean compilation with _MIPS_BSD_API_LP32_64CLEAN set.
 2000-07-10 23:21:16 +00:00
jeffs
010c198b37 In setregs() flush sigreturn trampoline code from the d (MIPS3) and i cache. 
Tested on geocast RM5231 platform.  This fixes a race in
regress/sys/kern/sigtramp.  Some other ports do the same thing.
 2000-07-10 21:12:13 +00:00
uch
e8ebb2a377 use mips3 cache op. 
invalidate -> write-back invalidate
(although NetBSD/hpcmips run on write-through mode.)
suggested by cgd.
 2000-07-10 16:23:18 +00:00
cgd
a5c13f9ad4 Kwality control: 
* put #includes of opt headers and headers to get protos used by
  net/netisr_dispatch.h in net/netisr.h (if !defined(_LOCORE)) (rather than
  in netisr_dispatch.h itself, and potentially nowhere, respectively).
* require netisr.h to be included before netisr_dispatch.h.
* minor additional cleanup of both netisr.h and netisr_dispatch.h.
* clean up uses to remove now-unnecessary header file inclusions, and
  local prototypes of the fns.
* convert netisr dispatch implementations which didn't use
  netisr_dispatch.h (pc532) to use it.
 2000-07-02 04:40:33 +00:00
mrg
28d898391b remove include of <vm/vm.h>. <vm/vm.h> -> <uvm/uvm_extern.h> 2000-06-29 08:10:45 +00:00
cgd
7e975cacbe un-__P, clean up spacing a little bit, put fwd struct decl(s) near top 
rather than embedded.  no functional changes.
 2000-06-29 06:00:43 +00:00
kleink
bb2ed0f487 G/c _BSD_INTPTR_T_ and _BSD_UINTPTR_T_. 2000-06-27 05:53:22 +00:00
kleink
47b5c5e3b1 Resolve some formatting nits; add __intptr_t and __uintptr_t. 2000-06-27 04:58:51 +00:00
kleink
e695f72a2e Add <machine/int_types.h>, which provides namespace-pure definitions 
of exact-width integer types.
 2000-06-26 15:42:16 +00:00
mrg
4c698e84f6 <vm/vm_param.h> -> <uvm/uvm_param.h> 2000-06-26 14:58:58 +00:00
mrg
2f159a1bac remove/move more mach vm header files: 
<vm/pglist.h> -> <uvm/uvm_pglist.h>
	<vm/vm_inherit.h> -> <uvm/uvm_inherit.h>
	<vm/vm_kern.h> -> into <uvm/uvm_extern.h>
	<vm/vm_object.h> -> nothing
	<vm/vm_pager.h> -> into <uvm/uvm_pager.h>

also includes a bunch of <vm/vm_page.h> include removals (due to redudancy
with <vm/vm.h>), and a scattering of other similar headers.
 2000-06-26 14:20:25 +00:00
simonb
889c658b5b Change the kernel mmap interface so that the offset to map is an 
"off_t" and the return value is a "paddr_t" to allow mappings
at offsets past 2^31 bytes.  Somewhat inspired by FreeBSD, which
only changed the offset to a "vm_offset_t".

Includes updates for the i386, pc532 and sh3 mmmmap from Jason Thorpe.
 2000-06-26 04:55:19 +00:00
nisimura
472221aa39 Abandon {mips1,mips3}_TBRPL() which have little gain than TLBUpdate(). 2000-06-26 03:05:04 +00:00
nisimura
074a952030 Abandon {mips1,mips3}_TBRPL()s which have little gain. They were 
expected to be better than MachTLBUpdate(). After all, TLBUpdate()
is rather harmful and should be replaced with TBIS().
 2000-06-26 02:55:45 +00:00
kleink
133ea38323 Add a WEAK_ALIAS() macro. 2000-06-23 12:18:45 +00:00
soren
e7d8e5164a Remove extraneous mips1_TBRPL() prototype. 2000-06-22 05:00:48 +00:00
soren
78c90ae276 Fix pasto. 2000-06-21 19:39:32 +00:00
soda
76baab0725 3rd argument of TBRPL() is not paddr_t but PTE. 
XXX - mips3_TBRPL seems to be never called.
 2000-06-20 05:54:03 +00:00
soren
d78ff1cd5b Add mips3_write_config(). 2000-06-20 02:57:17 +00:00
cgd
942546fe30 cod: any of various bottom-dwelling fishes (family Gadidae, the cod 
family) that usually occur in cold marine waters and often have barbels
  and three dorsal fins.
code: a set of instructions for a computer.

The latter is more appropriate in the comment corrected here.
 2000-06-17 06:38:25 +00:00
cgd
79d0534b05 put cache op #defines up at the top of the file, so all cache ops can 
use them.  Rename them to match the names in See Mips Run; they're not
as orthogonal as values or'd together might make you think...  Finally,
actually use them for every bloody cache op.
 2000-06-17 01:35:28 +00:00
cgd
433fe9077e when printing the cpu_id (because it's unknown or not supported), 
print the whole PRID value.  Also, print the PRID value in addition to
the name, when the CPU is known (for data collection purposes).
 2000-06-15 23:39:14 +00:00
shin
5ded3d8a81 backout previous change. 
cache operation in cpu_fork() is necessary for CPU's which
detect virtual alias by hardware (ex. R4000 with secondary cache).
 2000-06-15 13:04:05 +00:00
soren
a8b7b64af8 Remove unnecessary HitFlushCache from cpu_fork(). From Toru Nishimura. 2000-06-14 22:17:59 +00:00
castor
751cd4ffb0 Profiling fixes from Ethan Solomita <ethan@geocast.com>. 
Merge Kernel MCOUNT and user MCOUNT.

The earlier code which was inserted to call _mcount in profiling
assembler routines is busted badly.  This gets it working with PIC
code and should work with any arbitrary assembler routine.
 2000-06-12 23:42:10 +00:00
soren
9f0da0dd16 Post a SIGFPE rather than SIGILL on floating point exceptions. 2000-06-10 02:43:49 +00:00
soda
1c2aa78d6b rename 
vad_to_pfn() -> mips_paddr_to_tlbpfn()
	pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.
 2000-06-09 06:30:35 +00:00
soda
2047c95e49 Decrease MIPS3_TLB_WIRED_ENTRIES from 8 to 2, 
and rename it to MIPS3_TLB_WIRED_UPAGES.
The value of wired register becomes variable on arc port,
and arc is the only mips3 port which uses the wired TLB entries 2..7.
 2000-06-09 06:06:57 +00:00
soda
26c2cf79c0 rename 
vad_to_pfn() -> mips_paddr_to_tlbpfn()
	pfn_to_vad() -> mips_tlbpfn_to_paddr()
as suggested by thorpej on port-mips Mar 27.
 2000-06-09 05:51:42 +00:00
soda
b1438dd751 make paddr_t 64bit on arc port by introducing _MIPS_PADDR_T_64BIT. 2000-06-09 04:36:43 +00:00
soda
f587c1c5bf typo in comment 2000-06-09 04:28:17 +00:00
soda
44769378c9 this header don't have to include <machine/locore.h>, 
include <mips/locore.h> instead.
 2000-06-09 04:24:22 +00:00
soda
9fee25ddfa USRIOSIZE had to be changed from 32 to 128, 
when MAXBSIZE was changed from 16KB to 64KB(MAXPHYS)
on <sys/param.h> revision 1.28.
 2000-06-09 04:18:19 +00:00
mhitch
afce867d15 Fix loadfpregs(): the register used to access the floating point registers 
was not getting loaded, and the floating point registers were being loaded
from the proc structure rather than the FP registers in the pcb.
 2000-06-08 04:47:13 +00:00
soren
a9aa2abf94 defopt SYSCALL_DEBUG. 2000-06-06 18:52:30 +00:00
soren
a2bda06df5 Typo. 2000-06-06 17:41:58 +00:00
soren
5e4ca4defb Rename RM5200 cache ops to mips3_*_2way in anticipation of using them 
for other CPUs with 2-way set associative L1 caches as well.
 2000-06-06 17:41:07 +00:00
soren
113f160717 R12K has 64 TLBs too. 2000-06-06 17:36:12 +00:00
soren
d8e5d1fa7d Add rnd(4) glue for the MIPS3 cycle counter. 2000-06-06 02:24:00 +00:00
jhawk
c063b64a2b Do not clear msgbufenabled in dumpsys(). Dump messages will now go to 
the message buffer. This can be invaluable in debugging if the dump
fails (assuming a persistant message buffer)
 2000-06-05 23:44:55 +00:00
shin
4a71a2a50f delete unnecessary 'extern ...' line. 2000-06-03 13:16:02 +00:00
shin
5d883bf68e make it compile with 'options SOFTFLOAT'. 2000-06-02 12:57:22 +00:00
thorpej
8c2d00aaeb Add a comment about needing to initialize p_cpu when multiple 
processors are supported.
 2000-05-31 05:09:14 +00:00
nisimura
48ef457a5f Leave fpcurproc NULL for Vr4100/TX3900. It's solely for delayed lazy 
FPA.  fp.S is free from fpcurproc references for SOFTFLOAT case.
 2000-05-31 01:11:58 +00:00
nisimura
788c728dbd Replace fpcurproc->p_addr-> references with curpcb->. 2000-05-31 00:59:27 +00:00