write operations appear to lose scsi interrupts and causes timeouts.
changes in this checkin include:
a nextdma bugfix causing a diagnostic check to erroneously trigger
Changed tail strategy to only use tail buffer for the minimal end slop
changed expected write dma overrun to 32 bytes.
turned on nextdma diagnostic check for dma end address since it
no longer gets triggerred by ethernet dma and helps debug scsi dma.
Added esp debugging printout and support.
a filesystem, but is not stable enough yet for general use.
increased priority of ethernet interrupts, mostly useful to aid debugging
of scsi interrupts while using an nfs disk.
added additional debugging output in the next dma driver.
perform extranneous cache flushes/purges before dma reads/ after dma writes
to aid debugging of scsi dma.
Make the initializer for BAUDLO depend on PCLK directly; it was incorrect on
some ports where PCLK is not 4.9152MHz.
XXX Is the default value actually used?
command (unlock for sd and cd) if no other partitions are open, return
EBUSY otherwise. DIOCEJECT will have the old semantic if its argument is not
0. The old ioctl has been renamed to ODIOCEJECT for binary compatibility.
it still probes the disks ok, but is having trouble with 0xdeadbeef
in buffers read from the disk. Suspected problems with DMA alignment
and toggling the secret ninja dma control register
cache). This helps to avoid cache alias problems, and can improve performance
in the case where physical pages have multiple mappings (since the pages will
not have to be marked cache-inhibited).
This is done on a physical page size basis, instead of virtual (as the
(on vax yet non-existing) bus_* routines does). This is similar to the
way uba allocation is done.
remove check for normal chaining interrupts and add check for combined chaining interrupts
only when used with a tail chain. This allows scsi to work for short unaligned buffers
and large aligned buffers.
with different flags from dosboot and biosboot. Although right now this
does not make a difference because we are building the libraries twice,
it can make a difference when we share the builds.
loadfile.h contains macros that are supposed to be MD, but loadfile.c is now MI.
Fixes:
- a.out support
- pass information values via an array not global variables
- don't assume that you can access memory directly.
- remove MD parts
- remove some printfs.
XXX: loadfile.c needs to be moved somewhere where other ports can use it.
XXX2: read() routines on the i386 don't appear to set errno on failure.
Actually the current ddb_init interface sucks, since there is no
magic number for a.out and it applies heuristics. It would be nice
if the boot blocks passed more info.
on 64 bit register that's not correctly signed extended. The R4x00 support
works again on DECstations. A similar change to the XTLBMiss handler probably
needs to be made, but I have not done that since I am unable to test any
changes to that.
Also re-order a couple of instructions to allow for delay with mfc0.
Add lk_bell() to ring keyboard audible bell (for rcons bell).
Add LK_KEY_CLICK option to reset keyboard and enable keyclick.
(off by default since theres no way to control it from userland yet).
This fix removes putting 0xfeedbeef in the unused restart registers.
When that was done, the machine would panic after a short while
with 0xfeedbeef in the normal dma buffer registers. A restart
cycle is probably hapenning without an interrupt or something.
there are no pages available immediately to use as a PT page, don't
just roll over and die. Only do that if we're the kernel pmap (shouldn't
happen very ofter [ever?!], and I'm not certain we're guaranteed valid
thread context when operating on the kernel pmap). For user pmaps, wait
for the pagedaemon to wake us up when more free pages are available.
while a larger message buffer size might be a good idea (even as the
default), the existing definition here was way too large and was, in
fact, accidental!
+ Don't use our own "clean" and "depend" targets
+ "make depend" works
+ Only include each include path once on compile lines
+ Clean up include file names
+ Don't build a separate libdrive.a, just specify driver source files
+ Use "make print-objdir" instead of old "printf ... | make -f-"
+ Remove more unnecessary targets, variables and other cruft
Still builds identical bootblocks to 1.3.3 with gcc, still too large
with egcs.
dec_boot.h, dec_exec.h & dec_prom.h were copied via respository
copy to sys/arch/pmax/stand/libsa.
+ dependency on libsa works
+ set and use BINDIR/BINMODE
+ don't pull in sys/lib/lib{sa,kern}/Makefile.inc (``make clean''
doesn't make empty lib/{sa,kern} directories in each
directory/obj dir).
+ remove unnecessary targets, variables and other cruft
+ wrap lines at 80 chars
Re-ordering SRCS line in libsa/Makefile to a more logical sequence
(alphabetical by source dir) results in a libsa.a with archive members
in a different order, and a resultant bootrz that differs from the 1.3.3
bootrz. Untested as yet, so left in but commented out.
Also, _don't_ install the bootblocks (as per intent of previous commit)
or our own small libsa(!).
2.7.2.2-myc2 (and produces _identical_ bootblocks with the 1.3.3
bootblocks which weren't in the tree), but egcs 1.1.1 builds a ufs.o
that's about a 100 bytes too big, and it busts the 7.5k we've got for
bootrz.
Still needs cleanup - the Makefiles could be better/cleaner, and doesn't
install yet (because of above problem). At least there's something to
work with now.
Note that we have our own versions of a lot of the sys/lib/libsa
routines which are less functional/smaller.
if it contained a "19" before. There are machines (in particular PS/2
descendants) which have a checksum at this place.
Introduce a patchable kernel variable "rtc_update_century" to modify
the behaviour: 1="always update" (for testing and if one wants to set
the clock back) or -1="never touch".
- Fix an error in mips3_cpu_switch_resume(); ASID was not set correctly.
- Remove global variable 'curpcb' reference in mips1_proc_trampoline().
- Restore 'cpuregs.h'.
* Add the correct version of locore_mips1.S [ See previous revision for
description of changes ]
* Use defopt'ed MIPS3_L2CACHE_ABSENT in mips_machdep.c and pmap.c
to avoid generating extraneous code.
* GC pmap_set_referenced in pmap.c
minor of libc and the major of libutil). For little-endian architectures
merge the bnswap() assembly versions with nto* and hton* using symbols
aliasing. Use symbol renaming for the bswap function in this case to avoid
namespace pollution.
Declare bswap* in machine/bswap.h, not machine/endian.h. For little-endian
machines, common code for inline macros go in machine/byte_swap.h
Sync libkern with libc.
Adjust #include in kernel sources for machine/bswap.h.
Affected files:
include/mips_param.h, include/pcb.h,
mips/locore_mips1.S, mips/locore_mips3.S,
mips/mips_machdep.c, mips/vm_machdep.c
Issue:
So far, NetBSD/mips has not successfully got rid of fixed-address
kernel stack. USPACE (two 4KB pages) of each process has two distinct
KSEG2 addresses, both refer to a single physical storage; one address
for fixed range [ UADDR .. KERNELSTACK ), and another for "normal" KSEG2
address which was allocated by kernel memory manager and unique to each
others of processes.
"Doubly mapped" USPACE complicates context switch. Both address ranges
have to be managed with a special care of "wired" TLB entries which
are never replaced until next context switch to ensure no TLB miss for
USPACE access. It's equally crumbersome that MIPS processor's cache
machinary gets be confused about USPACE contents because there are two
distinct KSEG2 addresses to manipulate one physical storage.
Solution:
Purge KERNELSTACK constant for kernel stack pointer and replace
it with process unique values. Kernel stack bottom is located at
'curproc->p_addr + USPACE'. Context switch is simplified as it unloads
half of TLB hardwiring burden. It just manages the unique KSEG2 address
of each USPACE to be wired. As the side effect, switch_exit() has no
MIPS processor ISA dependent code anymore. It switchs kernel stack to
proc0's USPACE which has KSEG0 address and no need of TLB entry.
* Extensive use of 'genassym.cf'
To hide target port dependent and/or processor register size dependent
constants from assembler routines, 'genassym.cf' now has an extentive
set of definitions for various constants and offset values of
structural objects. This change will contribute possible NetBSD/mips64
portability too.
* Separation and rename of locore_r2000/_r4000.S
Those files are now indepedent standalones from locore.S to ease
maintainance works, and renamed to match MIPS processor ISA version.
* Changes in kernel mode exception handlers
Kernel mode exception handlers hold exception contexts by pushing a
certain set of register values on stack for resuming kernel mode
processing. This context is now represented with 'struct trapframe',
which is smaller than full scale (user mode) exception context 'struct
frame'. Stack consumption of kernel mode exception services is now
similar to 4.4BSD/mips.
* Relocation of exception frame
User mode context 'struct frame' is moved to the very bottom of kernel
stack at 'curproc->p_addr + USPACE - sizeof(struct frame)' This change
saves a bit of instructions on every return to user processes as it
eliminates reference to global variable 'curpcb' each time.
* Refurblished DDB backtrace routine
It's a growing concern to maintain stacktrace() code correctly. It
could be simplified by enforcing special arrangements for some of
obscure locore routines which violate usual coding conventions.
New backtrace code searchs for certain instructions peculiar to any of
function tails. Specifically, "jr ra" for normal function returns, "jr
k0" for MIPS1 exception handlers and "eret" for MIPS3 handlers.
* Support for 64-bit safe user code
Affected Files:
${ARCH}/include/pubassym.cf lib/libc/arch/mips/gen/*setjmp*
include/setjmp.h mips/include/[lots] mips/mips/[lots]
Solution:
We define macros REG_L/REG_S and SZREG for loading and storing
registers and for the size of registers. The exact meaning
of these is controlled by a macro (currently _MIPS64) which
allows one to treat the registers as either 32-bit or 64-bit.
There are data types mips_reg_t and mips_fpreg_t which represent
the true register sizes, and avoid confusing register_t.
We needed a way to dynamically gen the structure sizes of things
like sigcontext for setjmp.h, so we defined a pubassym.cf for
libc routines like setjmp and longjmp.
NetBSD/mips allows ${ARCH}'s to be defined which preserve
all 64-bits of registers across user context switches. There
are still a few niceties to clean up for kernel mode context
switches.
* Support for QED 52xx processors
Affected Files:
mips/locore_mips3.S mips/pmap.c include/locore.h
Issue:
The QED 52xx family of processors are targeted at low cost
embedded systems, (i.e. CPUs ~$30) for systems like routers, printers,
etc. We have added preliminary support for some of the idiosyncrasies
of this processor, e.g. no L2 cache, etc. More work needs to be
done here because with a modest 2-way L1 cache, some of the rampant
flushing has significant performance implications. However,
it doesn't crash, which is a start.
Solution:
A routine for flushing the cache based on virtual addresses was added;
a routine which deals with the two-way set associativity of the
5230 L1 cache was added, accomodations to 5230's instruction hazards
were added.
* TLB Miss code for mips3/mips4 processors cleaned up significantly.
Affected Files:
mips/locore_mips3.S mips/vm_machdep.c include/locore.h mips_machdep.c
Issue:
The TLB Miss handler exceeded the allowed size, which wasn't
a problem because there was no handler for when the processor
was in 64-bit mode. The handler for invalid TLB exceptions
also appears to have much vestigial code, which made it
difficult to understand.
Solution:
Use the XCONTEXT register to store a pointer to the segment
map table, this coupled with removing some dead code allows
the handlers to fit.
decoupled from long or int or long long. Define macros in asm.h to facilitate
choosing these on a port by port basis.
* Create <machine/pubassym.h> mechanism to allow jmp_buf structure size
to be calculated at system build time.
* Define _MIPS_BSD_SIM macro which specifies what calling style is appropritae
for the architecture. For 64-bit oriented systems set the Status Register
to allow 64-bit instructions.
* Remove UADDR related macros because kernel U structure is now mapped
normally.
* Separate cpu.h into cpu.h and cpuarch.h to keep things neat.
* Add support for QED 52xx processors
sakamoto