overhalt of scsi driver.
it still probes the disks ok, but is having trouble with 0xdeadbeef in buffers read from the disk. Suspected problems with DMA alignment and toggling the secret ninja dma control register
This commit is contained in:
dbj
parent
be1af660c0
commit
3e0d6eb0b4
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@ -1,4 +1,4 @@
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/* $NetBSD: esp.c,v 1.17 1999/02/02 14:04:53 dbj Exp $ */
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/* $NetBSD: esp.c,v 1.18 1999/02/03 20:44:43 dbj Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -332,15 +332,34 @@ espattach_intio(parent, self, aux)
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nextdma_config(&esc->sc_scsi_dma);
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nextdma_init(&esc->sc_scsi_dma);
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#if 0
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/* Turn on target selection using the `dma' method */
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ncr53c9x_dmaselect = 1;
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#else
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ncr53c9x_dmaselect = 0;
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#endif
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esc->sc_datain = -1;
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esc->sc_dmaaddr = 0;
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esc->sc_dmalen = 0;
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esc->sc_dmasize = -1;
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esc->sc_loaded = 0;
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esc->sc_begin = 0;
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esc->sc_begin_size = 0;
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{
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int error;
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if ((error = bus_dmamap_create(esc->sc_scsi_dma.nd_dmat,
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sc->sc_maxxfer, 1, sc->sc_maxxfer,
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0, BUS_DMA_ALLOCNOW, &esc->sc_dmamap)) != 0) {
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panic("%s: can't create i/o DMA map, error = %d",
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0, BUS_DMA_ALLOCNOW, &esc->sc_main_dmamap)) != 0) {
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panic("%s: can't create main i/o DMA map, error = %d",
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sc->sc_dev.dv_xname,error);
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}
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}
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esc->sc_main = 0;
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esc->sc_main_size = 0;
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{
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int error;
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@ -351,24 +370,11 @@ espattach_intio(parent, self, aux)
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sc->sc_dev.dv_xname,error);
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}
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}
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esc->sc_tail = 0;
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esc->sc_tail_size = 0;
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}
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#if 0
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/* Turn on target selection using the `dma' method */
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ncr53c9x_dmaselect = 1;
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#else
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ncr53c9x_dmaselect = 0;
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#endif
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esc->sc_datain = -1;
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esc->sc_slop_bgn_addr = 0;
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esc->sc_slop_bgn_size = 0;
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esc->sc_slop_end_addr = 0;
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esc->sc_slop_end_size = 0;
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esc->sc_dmamap_loaded = 0;
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esc->sc_tail = 0;
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esc->sc_tail_size = 0;
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/* Establish interrupt channel */
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isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc,
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NEXT_I_IPL(NEXT_I_SCSI), 0);
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@ -481,116 +487,44 @@ esp_dma_reset(sc)
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}
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#endif
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/* Clear the DMAMOD bit in the DCTL register: */
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if (esc->sc_datain) {
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMARD);
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} else {
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB);
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}
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB);
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nextdma_reset(&esc->sc_scsi_dma);
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if (esc->sc_dmamap_loaded) {
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/* fixing this is slightly complicated since multiple maps may be loaded,
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* and the esc->sc_dmamap_loaded variable only indicates the most recent one.
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*/
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panic("invoking completed callbacks upon esp_dma_reset is not yet implemented");
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esc->sc_datain = -1;
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esc->sc_dmaaddr = 0;
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esc->sc_dmalen = 0;
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esc->sc_dmasize = -1;
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esp_dmacb_completed(esc->sc_dmamap,sc);
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esp_dmacb_completed(esc->sc_tail_dmamap,sc);
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esc->sc_loaded = 0;
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esc->sc_begin = 0;
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esc->sc_begin_size = 0;
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if (esc->sc_main_dmamap->dm_mapsize) {
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bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap);
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}
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esc->sc_main = 0;
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esc->sc_main_size = 0;
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esp_dmacb_shutdown(sc); /* this will clean up */
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if (esc->sc_tail_dmamap->dm_mapsize) {
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bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap);
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}
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esc->sc_tail = 0;
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esc->sc_tail_size = 0;
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}
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int
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esp_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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int trans;
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int resid;
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int datain;
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struct esp_softc *esc = (struct esp_softc *)sc;
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datain = esc->sc_datain;
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panic("esp_dma_intr resetting dma\n");
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DPRINTF(("esp_dma_intr resetting dma\n"));
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/* If the dma hasn't finished when we are in a scsi
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* interrupt. Then, "Houston, we have a problem."
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* Stop DMA and figure out how many bytes were transferred
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*/
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esp_dma_reset(sc);
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resid = 0;
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/*
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* If a transfer onto the SCSI bus gets interrupted by the device
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* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
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* as residual since the ESP counter registers get decremented as
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* bytes are clocked into the FIFO.
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*/
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if (! datain) {
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resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF);
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if (resid) {
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NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
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NCRCMD(sc, NCRCMD_FLUSH);
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DELAY(1);
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}
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}
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if ((sc->sc_espstat & NCRSTAT_TC) == 0) {
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/*
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* `Terminal count' is off, so read the residue
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* out of the ESP counter registers.
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*/
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resid += (NCR_READ_REG(sc, NCR_TCL) |
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(NCR_READ_REG(sc, NCR_TCM) << 8) |
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((sc->sc_cfg2 & NCRCFG2_FE)
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? (NCR_READ_REG(sc, NCR_TCH) << 16)
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: 0));
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if (resid == 0 && esc->sc_dmasize == 65536 &&
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(sc->sc_cfg2 & NCRCFG2_FE) == 0)
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/* A transfer of 64K is encoded as `TCL=TCM=0' */
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resid = 65536;
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}
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trans = esc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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#if 0
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/*
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* This situation can happen in perfectly normal operation
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* if the ESP is reselected while using DMA to select
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* another target. As such, don't print the warning.
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*/
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printf("%s: xfer (%d) > req (%d)\n",
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esc->sc_dev.dv_xname, trans, esc->sc_dmasize);
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#endif
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trans = esc->sc_dmasize;
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}
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NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
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NCR_READ_REG(sc, NCR_TCL),
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NCR_READ_REG(sc, NCR_TCM),
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(sc->sc_cfg2 & NCRCFG2_FE)
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? NCR_READ_REG(sc, NCR_TCH) : 0,
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trans, resid));
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#ifdef ESP_DEBUG
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if (esp_debug) esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize);
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#ifdef DIAGNOSTIC
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panic("%s: esp_dma_intr shouldn't be invoked.\n", sc->sc_dev.dv_xname);
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#endif
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*esc->sc_dmalen -= trans;
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*esc->sc_dmaaddr += trans;
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return 0;
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return -1;
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}
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int
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@ -611,7 +545,10 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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int *v = (int *)(*addr);
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int i;
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for(i=0;i<((*len)/4);i++) v[i] = 0xdeadbeef;
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v = (int *)(&(esc->sc_tailbuf[0]));
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for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed;
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}
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#endif
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DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize));
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@ -626,12 +563,12 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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#ifdef DIAGNOSTIC
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if ((esc->sc_datain != -1) ||
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(esc->sc_dmamap->dm_mapsize != 0) ||
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(esc->sc_dmamap_loaded != 0)) {
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(esc->sc_main_dmamap->dm_mapsize != 0) ||
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(esc->sc_tail_dmamap->dm_mapsize != 0)) {
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panic("%s: map already loaded in esp_dma_setup\n"
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"\tdatain = %d\n\tmapsize=%d\n\tloaed = %d",
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sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap->dm_mapsize,
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esc->sc_dmamap_loaded);
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"\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d",
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sc->sc_dev.dv_xname, esc->sc_datain,
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esc->sc_main_dmamap->dm_mapsize,esc->sc_tail_dmamap->dm_mapsize);
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}
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#endif
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@ -641,16 +578,12 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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esc->sc_dmalen = len;
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esc->sc_dmasize = *dmasize;
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/* Deal with DMA alignment issues, by stuffing the FIFO.
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* This assumes that if bus_dmamap_load is given an aligned
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* buffer, then it will generate aligned hardware addresses
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* to give to the device. Perhaps that is not a good assumption,
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* but it is probably true. [dbj@netbsd.org:19980719.0135EDT]
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*/
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{
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int slop_bgn_size; /* # bytes to be fifo'd at beginning */
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int slop_end_size; /* # bytes to be fifo'd at end */
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esc->sc_loaded = 0;
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{
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size_t slop_bgn_size; /* # bytes to be fifo'd at beginning */
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size_t slop_end_size; /* # bytes to be transferred in tail buffer */
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{
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u_long bgn = (u_long)(*esc->sc_dmaaddr);
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u_long end = (u_long)(*esc->sc_dmaaddr+esc->sc_dmasize);
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@ -664,56 +597,67 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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* as would happen for a very short dma buffer, also
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* for short buffers, just stuff the entire thing in the tail
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*/
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if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize) ||
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(esc->sc_dmasize <= ESP_DMA_MAXTAIL)) {
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if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize)
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#if 1
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|| (esc->sc_dmasize <= ESP_DMA_MAXTAIL)
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#endif
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)
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{
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slop_bgn_size = 0;
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slop_end_size = esc->sc_dmasize;
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}
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esc->sc_slop_bgn_addr = *esc->sc_dmaaddr;
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esc->sc_slop_bgn_size = slop_bgn_size;
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esc->sc_slop_end_addr = (*esc->sc_dmaaddr+esc->sc_dmasize)-slop_end_size;
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esc->sc_slop_end_size = slop_end_size;
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}
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/* Load the normal DMA map */
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if (esc->sc_dmasize-(esc->sc_slop_bgn_size+esc->sc_slop_end_size)) {
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int error;
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error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat,
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esc->sc_dmamap,
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*esc->sc_dmaaddr+esc->sc_slop_bgn_size,
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esc->sc_dmasize-(esc->sc_slop_bgn_size+esc->sc_slop_end_size),
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NULL, BUS_DMA_NOWAIT);
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if (error) {
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panic("%s: can't load dma map. error = %d",
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sc->sc_dev.dv_xname, error);
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}
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}
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/* Now set up the tail dma buffer, including alignment. */
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if (esc->sc_slop_end_size) {
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esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+esc->sc_slop_end_size)-esc->sc_slop_end_size;
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/* If the beginning of the tail is not correctly aligned,
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* we have no choice but to align the start, which might then unalign the end.
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*/
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esc->sc_tail = DMA_ALIGN(caddr_t,esc->sc_tail);
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/* So therefore, we change the tail size to be end aligned again. */
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esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+esc->sc_slop_end_size)-esc->sc_tail;
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/* initialize the fifo buffer */
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if (slop_bgn_size) {
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esc->sc_begin = *esc->sc_dmaaddr;
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esc->sc_begin_size = slop_bgn_size;
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} else {
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esc->sc_begin = 0;
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esc->sc_begin_size = 0;
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}
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/* Load the normal DMA map */
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{
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int error;
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error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat,
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esc->sc_tail_dmamap,
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esc->sc_tail, esc->sc_tail_size,
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NULL, BUS_DMA_NOWAIT);
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if (error) {
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panic("%s: can't load dma map. error = %d",
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sc->sc_dev.dv_xname, error);
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esc->sc_main = *esc->sc_dmaaddr+slop_bgn_size;
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esc->sc_main_size = (esc->sc_dmasize)-(slop_end_size+slop_bgn_size);
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if (esc->sc_main_size) {
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int error;
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error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat,
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esc->sc_main_dmamap,
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esc->sc_main, esc->sc_main_size,
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NULL, BUS_DMA_NOWAIT);
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if (error) {
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panic("%s: can't load main dma map. error = %d, addr=0x%08x, size=0x%08x",
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sc->sc_dev.dv_xname, error,esc->sc_main,esc->sc_main_size);
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}
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} else {
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esc->sc_main = 0;
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}
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}
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/* Load the tail DMA map */
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if (slop_end_size) {
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esc->sc_tail = DMA_ENDALIGN(caddr_t,esc->sc_tailbuf+slop_end_size)-slop_end_size;
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/* If the beginning of the tail is not correctly aligned,
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* we have no choice but to align the start, which might then unalign the end.
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*/
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esc->sc_tail = DMA_ALIGN(caddr_t,esc->sc_tail);
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/* So therefore, we change the tail size to be end aligned again. */
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esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail;
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{
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int error;
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error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat,
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esc->sc_tail_dmamap,
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esc->sc_tail, esc->sc_tail_size,
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NULL, BUS_DMA_NOWAIT);
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if (error) {
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panic("%s: can't load tail dma map. error = %d, addr=0x%08x, size=0x%08x",
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sc->sc_dev.dv_xname, error,esc->sc_tail,esc->sc_tail_size);
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}
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}
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}
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} else {
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esc->sc_tail = 0;
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esc->sc_tail_size = 0;
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}
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return (0);
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@ -725,11 +669,19 @@ esp_dma_go(sc)
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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DPRINTF(("esp_dma_go(datain = %d)\n",esc->sc_datain));
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DPRINTF(("%s: esp_dma_go(datain = %d)\n",
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sc->sc_dev.dv_xname, esc->sc_datain));
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DPRINTF(("\tbgn slop = %d\n\tend slop = %d\n\tmapsize = %d\n",
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esc->sc_slop_bgn_size,esc->sc_slop_end_size,
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esc->sc_dmamap->dm_mapsize));
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DPRINTF(("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n",
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sc->sc_dev.dv_xname,
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*esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize));
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DPRINTF(("%s: begin = 0x%08x, size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size));
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DPRINTF(("%s: main = 0x%08x, size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size));
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DPRINTF(("%s: tail = 0x%08x, size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size));
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#ifdef DIAGNOSTIC
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{
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@ -738,46 +690,34 @@ esp_dma_go(sc)
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}
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#endif
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if (esc->sc_datain) {
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#if defined(DIAGNOSTIC)
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if ((esc->sc_begin_size == 0) &&
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(esc->sc_main_dmamap->dm_mapsize == 0) &&
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(esc->sc_tail_dmamap->dm_mapsize == 0)) {
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panic("%s: No DMA requested!",sc->sc_dev.dv_xname);
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}
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||||
#endif
|
||||
|
||||
/* Stuff the fifo with the begin buffer */
|
||||
if (esc->sc_datain) {
|
||||
int i;
|
||||
for(i=0;i<esc->sc_slop_bgn_size;i++) {
|
||||
esc->sc_slop_bgn_addr[i]=NCR_READ_REG(sc, NCR_FIFO);
|
||||
for(i=0;i<esc->sc_begin_size;i++) {
|
||||
esc->sc_begin[i]=NCR_READ_REG(sc, NCR_FIFO);
|
||||
}
|
||||
} else {
|
||||
int i;
|
||||
for(i=0;i<esc->sc_slop_bgn_size;i++) {
|
||||
NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_slop_bgn_addr[i]);
|
||||
for(i=0;i<esc->sc_begin_size;i++) {
|
||||
NCR_WRITE_REG(sc, NCR_FIFO, esc->sc_begin[i]);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
{
|
||||
int n = NCR_READ_REG(sc, NCR_FFLAG);
|
||||
DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5));
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(DIAGNOSTIC)
|
||||
if ((esc->sc_dmamap->dm_mapsize == 0) && (esc->sc_tail_dmamap->dm_mapsize == 0)) {
|
||||
panic("%s: No DMA requested!");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* if we are a dma write cycle, copy the end slop */
|
||||
if (esc->sc_datain == 0) {
|
||||
memcpy(esc->sc_tail,esc->sc_slop_end_addr,esc->sc_slop_end_size);
|
||||
memcpy(esc->sc_tail,
|
||||
(*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size),
|
||||
(esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size)));
|
||||
}
|
||||
|
||||
#if defined(DIAGNOSTIC)
|
||||
/* This would happen if we try to transfer unaligned buffers
|
||||
* that are greater than ESP_DMA_MAXTAIL. Is that ever expected?
|
||||
*/
|
||||
if ((esc->sc_dmamap->dm_mapsize) &&
|
||||
(esc->sc_tail_dmamap->dm_mapsize)) {
|
||||
panic("combined regular and tail map is currently broken");
|
||||
}
|
||||
#endif
|
||||
|
||||
nextdma_start(&esc->sc_scsi_dma,
|
||||
(esc->sc_datain ? DMACSR_READ : DMACSR_WRITE));
|
||||
|
||||
|
|
@ -788,6 +728,7 @@ esp_dma_go(sc)
|
|||
NCR_WRITE_REG(sc, ESP_DCTL,
|
||||
ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void
|
||||
|
|
@ -817,7 +758,7 @@ esp_dmacb_continue(arg)
|
|||
struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg;
|
||||
struct esp_softc *esc = (struct esp_softc *)sc;
|
||||
|
||||
DPRINTF(("esp dma continue\n"));
|
||||
DPRINTF(("%s: dma continue\n",sc->sc_dev.dv_xname));
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) {
|
||||
|
|
@ -825,34 +766,29 @@ esp_dmacb_continue(arg)
|
|||
sc->sc_dev.dv_xname,esc->sc_datain);
|
||||
}
|
||||
#endif
|
||||
switch(esc->sc_dmamap_loaded) {
|
||||
case 0:
|
||||
if (esc->sc_dmamap->dm_mapsize) {
|
||||
bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap,
|
||||
0, esc->sc_dmamap->dm_mapsize,
|
||||
|
||||
if ((!(esc->sc_loaded & ESP_LOADED_MAIN)) &&
|
||||
(esc->sc_main_dmamap->dm_mapsize)) {
|
||||
DPRINTF(("%s: Loading main map\n",sc->sc_dev.dv_xname));
|
||||
bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap,
|
||||
0, esc->sc_main_dmamap->dm_mapsize,
|
||||
(esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
|
||||
esc->sc_dmamap_loaded = 1;
|
||||
DPRINTF(("Loading primary map\n"));
|
||||
return(esc->sc_dmamap);
|
||||
}
|
||||
/* Fallthrough */
|
||||
case 1:
|
||||
if (esc->sc_tail_dmamap->dm_mapsize) {
|
||||
esc->sc_loaded |= ESP_LOADED_MAIN;
|
||||
return(esc->sc_main_dmamap);
|
||||
}
|
||||
|
||||
if ((!(esc->sc_loaded & ESP_LOADED_TAIL)) &&
|
||||
(esc->sc_tail_dmamap->dm_mapsize)) {
|
||||
DPRINTF(("%s: Loading tail map\n",sc->sc_dev.dv_xname));
|
||||
bus_dmamap_sync(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap,
|
||||
0, esc->sc_tail_dmamap->dm_mapsize,
|
||||
(esc->sc_datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
|
||||
esc->sc_dmamap_loaded = 2;
|
||||
DPRINTF(("Loading tail map\n"));
|
||||
esc->sc_loaded |= ESP_LOADED_TAIL;
|
||||
return(esc->sc_tail_dmamap);
|
||||
}
|
||||
/* Fallthrough */
|
||||
case 2:
|
||||
DPRINTF(("Not loading map\n"));
|
||||
return(0);
|
||||
default:
|
||||
panic("%s: Unexpected sc_dmamap_loaded (%d) in continue_cb",
|
||||
sc->sc_dev.dv_xname,esc->sc_dmamap_loaded);
|
||||
}
|
||||
|
||||
DPRINTF(("%s: not loading map\n",sc->sc_dev.dv_xname));
|
||||
return(0);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -868,10 +804,10 @@ esp_dmacb_completed(map, arg)
|
|||
|
||||
#ifdef DIAGNOSTIC
|
||||
if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) {
|
||||
panic("%s: map not loaded in dma completed callback, datain = %d, loaded = %d",
|
||||
sc->sc_dev.dv_xname,esc->sc_datain,esc->sc_dmamap_loaded);
|
||||
panic("%s: invalid dma direction in completed callback, datain = %d",
|
||||
sc->sc_dev.dv_xname,esc->sc_datain);
|
||||
}
|
||||
if ((map != esc->sc_dmamap) && (map != esc->sc_tail_dmamap)) {
|
||||
if ((map != esc->sc_main_dmamap) && (map != esc->sc_tail_dmamap)) {
|
||||
panic("%s: unexpected completed map", sc->sc_dev.dv_xname);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -907,27 +843,46 @@ esp_dmacb_shutdown(arg)
|
|||
}
|
||||
#endif
|
||||
|
||||
if (esc->sc_dmamap->dm_mapsize) {
|
||||
bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_dmamap);
|
||||
}
|
||||
if (esc->sc_tail_dmamap->dm_mapsize) {
|
||||
bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap);
|
||||
/* First copy the tail dma buffer data for read transfers */
|
||||
if (esc->sc_datain == 1) {
|
||||
memcpy((*esc->sc_dmaaddr+esc->sc_begin_size+esc->sc_main_size),
|
||||
esc->sc_tail,
|
||||
(esc->sc_dmasize-(esc->sc_begin_size+esc->sc_main_size)));
|
||||
}
|
||||
|
||||
if (esc->sc_datain == 1) {
|
||||
memcpy(esc->sc_slop_end_addr,esc->sc_tail,esc->sc_slop_end_size);
|
||||
}
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
if (esp_debug) esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize);
|
||||
if (esp_debug) {
|
||||
printf("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n",
|
||||
sc->sc_dev.dv_xname,
|
||||
*esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize);
|
||||
esp_hex_dump(*(esc->sc_dmaaddr),esc->sc_dmasize);
|
||||
printf("%s: tail=0x%08lx,tailbuf=0x%08lx,tail_size=0x%08lx\n",
|
||||
sc->sc_dev.dv_xname,
|
||||
esc->sc_tail, &(esc->sc_tailbuf[0]), esc->sc_tail_size);
|
||||
esp_hex_dump(&(esc->sc_tailbuf[0]),sizeof(esc->sc_tailbuf));
|
||||
}
|
||||
#endif
|
||||
|
||||
esc->sc_datain = -1;
|
||||
esc->sc_slop_bgn_addr = 0;
|
||||
esc->sc_slop_bgn_size = 0;
|
||||
esc->sc_slop_end_addr = 0;
|
||||
esc->sc_slop_end_size = 0;
|
||||
esc->sc_dmamap_loaded = 0;
|
||||
esc->sc_dmaaddr = 0;
|
||||
esc->sc_dmalen = 0;
|
||||
esc->sc_dmasize = -1;
|
||||
|
||||
esc->sc_loaded = 0;
|
||||
|
||||
esc->sc_begin = 0;
|
||||
esc->sc_begin_size = 0;
|
||||
|
||||
if (esc->sc_main_dmamap->dm_mapsize) {
|
||||
bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_main_dmamap);
|
||||
}
|
||||
esc->sc_main = 0;
|
||||
esc->sc_main_size = 0;
|
||||
|
||||
if (esc->sc_tail_dmamap->dm_mapsize) {
|
||||
bus_dmamap_unload(esc->sc_scsi_dma.nd_dmat, esc->sc_tail_dmamap);
|
||||
}
|
||||
esc->sc_tail = 0;
|
||||
esc->sc_tail_size = 0;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
/* $NetBSD: espvar.h,v 1.6 1999/01/27 06:37:49 dbj Exp $ */
|
||||
/* $NetBSD: espvar.h,v 1.7 1999/02/03 20:44:43 dbj Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
|
|
@ -42,19 +42,36 @@ struct esp_softc {
|
|||
struct nextdma_config sc_scsi_dma;
|
||||
bus_space_tag_t sc_bst;
|
||||
bus_space_handle_t sc_bsh; /* the device registers */
|
||||
bus_dmamap_t sc_dmamap; /* i/o dma map */
|
||||
int sc_datain; /* dma direction for map */
|
||||
caddr_t sc_slop_bgn_addr; /* bytes to be fifo'd at beginning */
|
||||
caddr_t sc_slop_end_addr; /* bytes to be fifo'd at end */
|
||||
int sc_slop_bgn_size; /* # bytes to be fifo'd at beginning */
|
||||
int sc_slop_end_size; /* # bytes to be fifo'd at end */
|
||||
int sc_dmamap_loaded; /* 0=not loaded, 1=sc_dmamap, 2=sc_tail_dmamap */
|
||||
caddr_t *sc_dmaaddr;
|
||||
size_t *sc_dmalen;
|
||||
size_t sc_dmasize;
|
||||
|
||||
caddr_t *sc_dmaaddr; /* saved argument to esp_dma_setup */
|
||||
size_t *sc_dmalen; /* saved argument to esp_dma_setup */
|
||||
size_t sc_dmasize; /* saved argument to esp_dma_setup */
|
||||
int sc_datain; /* saved argument to esp_dma_setup */
|
||||
|
||||
#define ESP_LOADED_MAIN (0x01)
|
||||
#define ESP_LOADED_TAIL (0x02)
|
||||
|
||||
int sc_loaded; /* used by continue callback to remember
|
||||
* which dmamaps are already loaded.
|
||||
*/
|
||||
|
||||
/* To deal with begin alignment problems, we stuff the fifo
|
||||
* with a begin buffer
|
||||
*/
|
||||
caddr_t sc_begin; /* pointer to start io buf, NULL if invalid */
|
||||
size_t sc_begin_size; /* */
|
||||
|
||||
bus_dmamap_t sc_main_dmamap; /* i/o dma map */
|
||||
caddr_t sc_main; /* pointer to main io buf, NULL if invalid */
|
||||
size_t sc_main_size; /* aligned length of main io buf we are using */
|
||||
|
||||
/* To deal with end alignment problems, we copy the end of the dma
|
||||
* buffer into a "tail" buffer that we can control more carefully.
|
||||
* We then chain this extra buffer onto the end.
|
||||
*/
|
||||
#define ESP_DMA_MAXTAIL 128
|
||||
caddr_t sc_tail;
|
||||
size_t sc_tail_size;
|
||||
char sc_tailbuf[ESP_DMA_MAXTAIL+2*DMA_ENDALIGNMENT];
|
||||
bus_dmamap_t sc_tail_dmamap;
|
||||
caddr_t sc_tail; /* pointer into sc_tailbuf, NULL if invalid */
|
||||
size_t sc_tail_size; /* aligned length of tailbuf we are using */
|
||||
u_char sc_tailbuf[ESP_DMA_MAXTAIL+2*DMA_ENDALIGNMENT];
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue