Continue hacking on esp driver. Seems relatively stable in read only mode.
write operations appear to lose scsi interrupts and causes timeouts. changes in this checkin include: a nextdma bugfix causing a diagnostic check to erroneously trigger Changed tail strategy to only use tail buffer for the minimal end slop changed expected write dma overrun to 32 bytes. turned on nextdma diagnostic check for dma end address since it no longer gets triggerred by ethernet dma and helps debug scsi dma. Added esp debugging printout and support.
This commit is contained in:
dbj
parent
37fc22a21d
commit
f651d280fa
@ -1,4 +1,4 @@
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/* $NetBSD: esp.c,v 1.19 1999/02/13 09:44:50 dbj Exp $ */
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/* $NetBSD: esp.c,v 1.20 1999/02/14 10:19:51 dbj Exp $ */
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/*-
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* Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
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@ -113,7 +113,7 @@
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#include "espreg.h"
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#include "espvar.h"
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#if 1
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#ifdef DEBUG
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#define ESP_DEBUG
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#endif
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@ -133,6 +133,14 @@ bus_dmamap_t esp_dmacb_continue __P((void *arg));
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void esp_dmacb_completed __P((bus_dmamap_t map, void *arg));
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void esp_dmacb_shutdown __P((void *arg));
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#ifdef ESP_DEBUG
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char esp_dma_dump[5*1024] = "";
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struct ncr53c9x_softc *esp_debug_sc = 0;
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void esp_dma_store __P((struct ncr53c9x_softc *sc));
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void esp_dma_print __P((struct ncr53c9x_softc *sc));
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#endif
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/* Linkup to the rest of the kernel */
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struct cfattach esp_ca = {
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sizeof(struct esp_softc), espmatch_intio, espattach_intio
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@ -214,6 +222,10 @@ espattach_intio(parent, self, aux)
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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#ifdef ESP_DEBUG
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esp_debug_sc = sc;
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#endif
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esc->sc_bst = NEXT68K_INTIO_BUS_SPACE;
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if (bus_space_map(esc->sc_bst, NEXT_P_SCSI,
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ESP_DEVICE_SIZE, 0, &esc->sc_bsh)) {
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@ -342,7 +354,7 @@ espattach_intio(parent, self, aux)
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esc->sc_datain = -1;
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esc->sc_dmaaddr = 0;
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esc->sc_dmalen = 0;
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esc->sc_dmasize = -1;
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esc->sc_dmasize = 0;
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esc->sc_loaded = 0;
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@ -378,7 +390,7 @@ espattach_intio(parent, self, aux)
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/* Establish interrupt channel */
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isrlink_autovec((int(*)__P((void*)))ncr53c9x_intr, sc,
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NEXT_I_IPL(NEXT_I_SCSI), -1);
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NEXT_I_IPL(NEXT_I_SCSI), 0);
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INTR_ENABLE(NEXT_I_SCSI);
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/* register interrupt stats */
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@ -424,36 +436,51 @@ esp_dma_isintr(sc)
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int r = (INTR_OCCURRED(NEXT_I_SCSI));
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if (r) {
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DPRINTF(("esp_dma_isintr = 0x%b\n",
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(*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS));
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while (esp_dma_isactive(sc)) {
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{
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int s;
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s = spldma();
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DPRINTF(("esp_dma_isintr = 0x%b\n",
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(*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS));
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while (esp_dma_isactive(sc)) {
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#ifdef DIAGNOSTIC
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r = (INTR_OCCURRED(NEXT_I_SCSI));
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if (!r) panic("esp dma enabled but failed to flush");
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r = (INTR_OCCURRED(NEXT_I_SCSI));
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if (!r) panic("esp intr enabled but dma failed to flush");
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#endif
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if (esc->sc_datain) {
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH);
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD);
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} else {
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH);
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD);
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}
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{
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int nr;
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nr = nextdma_intr(&esc->sc_scsi_dma);
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if (nr) {
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DPRINTF(("nextma_intr = %d\n",nr));
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if (esc->sc_datain) {
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD | ESPDCTL_FLUSH);
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_DMARD);
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} else {
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD | ESPDCTL_FLUSH);
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NCR_WRITE_REG(sc, ESP_DCTL,
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ESPDCTL_20MHZ | ESPDCTL_INTENB | ESPDCTL_DMAMOD);
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}
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/* Really this code should only be used in polled mode */
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{
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int nr;
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nr = nextdma_intr(&esc->sc_scsi_dma);
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if (nr) {
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DPRINTF(("nextma_intr = %d\n",nr));
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}
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}
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}
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splx(s);
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}
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#ifdef DIAGNOSTIC
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r = (INTR_OCCURRED(NEXT_I_SCSI));
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if (!r) panic("esp intr not enabled after dma flush");
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#endif
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/* Clear the DMAMOD bit in the DCTL register, since if this
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* routine returns true, then the ncr53c9x_intr handler will
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* be called and needs access to the scsi registers.
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@ -497,7 +524,7 @@ esp_dma_reset(sc)
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esc->sc_datain = -1;
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esc->sc_dmaaddr = 0;
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esc->sc_dmalen = 0;
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esc->sc_dmasize = -1;
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esc->sc_dmasize = 0;
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esc->sc_loaded = 0;
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@ -547,6 +574,7 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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struct esp_softc *esc = (struct esp_softc *)sc;
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#ifdef DIAGNOSTIC
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#ifdef ESP_DEBUG
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/* if this is a read DMA, pre-fill the buffer with 0xdeadbeef
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* to identify bogus reads
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*/
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@ -557,7 +585,7 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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v = (int *)(&(esc->sc_tailbuf[0]));
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for(i=0;i<((sizeof(esc->sc_tailbuf)/4));i++) v[i] = 0xdeaffeed;
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}
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#endif
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#endif
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DPRINTF(("esp_dma_setup(0x%08lx,0x%08lx,0x%08lx)\n",*addr,*len,*dmasize));
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@ -573,14 +601,22 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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#ifdef DIAGNOSTIC
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if ((esc->sc_datain != -1) ||
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(esc->sc_main_dmamap->dm_mapsize != 0) ||
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(esc->sc_tail_dmamap->dm_mapsize != 0)) {
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(esc->sc_tail_dmamap->dm_mapsize != 0) ||
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(esc->sc_dmasize != 0)) {
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panic("%s: map already loaded in esp_dma_setup\n"
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"\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d",
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"\tdatain = %d\n\tmain_mapsize=%d\n\tail_mapsize=%d\n\tdmasize = %d",
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sc->sc_dev.dv_xname, esc->sc_datain,
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esc->sc_main_dmamap->dm_mapsize,esc->sc_tail_dmamap->dm_mapsize);
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esc->sc_main_dmamap->dm_mapsize,
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esc->sc_tail_dmamap->dm_mapsize,
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esc->sc_dmasize);
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}
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#endif
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/* we are sometimes asked to dma zero bytes, that's easy */
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if (*len <= 0) {
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return(0);
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}
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/* Save these in case we have to abort DMA */
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esc->sc_datain = datain;
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esc->sc_dmaaddr = addr;
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@ -602,18 +638,12 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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slop_end_size = (end % DMA_ENDALIGNMENT);
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}
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/* Force a minimum slop end size to guarantee correct use of tailbuf
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* and provide for dma overrun
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*/
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slop_end_size += ESP_DMA_MAXTAIL;
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/* Check to make sure we haven't counted extra slop
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* as would happen for a very short dma buffer, also
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* for short buffers, just stuff the entire thing in the tail
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*/
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if ((slop_bgn_size+slop_end_size >= esc->sc_dmasize)
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#if 1
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#if 0
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|| (esc->sc_dmasize <= ESP_DMA_MAXTAIL)
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#endif
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)
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@ -665,8 +695,10 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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esc->sc_tail_size = DMA_ENDALIGN(caddr_t,esc->sc_tail+slop_end_size)-esc->sc_tail;
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/* @@@ next dma overrun lossage */
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if (!esc->sc_datain) esc->sc_tail_size += ESP_DMA_OVERRUN;
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if (!esc->sc_datain) {
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esc->sc_tail_size += 2*ESP_DMA_OVERRUN;
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}
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{
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int error;
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error = bus_dmamap_load(esc->sc_scsi_dma.nd_dmat,
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@ -687,60 +719,102 @@ esp_dma_setup(sc, addr, len, datain, dmasize)
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return (0);
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}
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#ifdef ESP_DEBUG
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/* For debugging */
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void
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esp_dma_store(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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char *p = &esp_dma_dump[0];
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p += sprintf(p,"%s: sc_datain=%d\n",sc->sc_dev.dv_xname,esc->sc_datain);
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p += sprintf(p,"%s: sc_loaded=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_loaded);
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if (esc->sc_dmaaddr) {
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p += sprintf(p,"%s: sc_dmaaddr=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmaaddr);
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} else {
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p += sprintf(p,"%s: sc_dmaaddr=NULL\n",sc->sc_dev.dv_xname);
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}
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if (esc->sc_dmalen) {
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p += sprintf(p,"%s: sc_dmalen=0x%08lx\n",sc->sc_dev.dv_xname,*esc->sc_dmalen);
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} else {
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p += sprintf(p,"%s: sc_dmalen=NULL\n",sc->sc_dev.dv_xname);
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}
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p += sprintf(p,"%s: sc_dmasize=0x%08x\n",sc->sc_dev.dv_xname,esc->sc_dmasize);
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p += sprintf(p,"%s: sc_begin = 0x%08x, sc_begin_size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size);
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p += sprintf(p,"%s: sc_main = 0x%08x, sc_main_size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size);
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{
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int i;
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bus_dmamap_t map = esc->sc_main_dmamap;
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p += sprintf(p,"%s: sc_main_dmamap. mapsize = 0x%08x, nsegs = %d\n",
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sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs);
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for(i=0;i<map->dm_nsegs;i++) {
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p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n",
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sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len);
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}
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}
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p += sprintf(p,"%s: sc_tail = 0x%08x, sc_tail_size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size);
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{
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int i;
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bus_dmamap_t map = esc->sc_tail_dmamap;
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p += sprintf(p,"%s: sc_tail_dmamap. mapsize = 0x%08x, nsegs = %d\n",
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sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs);
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for(i=0;i<map->dm_nsegs;i++) {
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p += sprintf(p,"%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n",
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sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len);
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}
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}
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}
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void
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esp_dma_print(sc)
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struct ncr53c9x_softc *sc;
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{
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esp_dma_store(sc);
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printf("%s",esp_dma_dump);
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}
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#endif
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void
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esp_dma_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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#ifdef DEBUG
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DPRINTF(("%s: esp_dma_go(datain = %d)\n",
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sc->sc_dev.dv_xname, esc->sc_datain));
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DPRINTF(("%s: dma_shutdown: addr=0x%08lx,len=0x%08lx,size=0x%08lx\n",
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sc->sc_dev.dv_xname,
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*esc->sc_dmaaddr, *esc->sc_dmalen, esc->sc_dmasize));
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DPRINTF(("%s: begin = 0x%08x, size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_begin, esc->sc_begin_size));
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DPRINTF(("%s: main = 0x%08x, size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_main, esc->sc_main_size));
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{
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int i;
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bus_dmamap_t map = esc->sc_main_dmamap;
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DPRINTF(("%s: main map. mapsize = 0x%08x, nsegs = %d\n",
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sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs));
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for(i=0;i<map->dm_nsegs;i++) {
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DPRINTF(("%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n",
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sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len));
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}
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}
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DPRINTF(("%s: tail = 0x%08x, size = 0x%08x\n",
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sc->sc_dev.dv_xname, esc->sc_tail, esc->sc_tail_size));
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{
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int i;
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bus_dmamap_t map = esc->sc_tail_dmamap;
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DPRINTF(("%s: tail map. mapsize = 0x%08x, nsegs = %d\n",
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sc->sc_dev.dv_xname, map->dm_mapsize, map->dm_nsegs));
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for(i=0;i<map->dm_nsegs;i++) {
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DPRINTF(("%s: map->dm_segs[%d]->ds_addr = 0x%08x, len = 0x%08x\n",
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sc->sc_dev.dv_xname, i, map->dm_segs[i].ds_addr, map->dm_segs[i].ds_len));
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}
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}
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#ifdef ESP_DEBUG
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if (esp_debug) esp_dma_print(sc);
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else esp_dma_store(sc);
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#endif
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#ifdef DIAGNOSTIC
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#ifdef ESP_DEBUG
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{
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int n = NCR_READ_REG(sc, NCR_FFLAG);
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DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5));
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DPRINTF(("%s: fifo size = %d, seq = 0x%x\n",
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sc->sc_dev.dv_xname,
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n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5));
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}
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#endif
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/* zero length dma transfers are boring, dmasize is probably -1 in those cases
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* because it was never set up by esp_dma_setup
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*/
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if (esc->sc_dmasize == 0) {
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return;
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}
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#if defined(DIAGNOSTIC)
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if ((esc->sc_begin_size == 0) &&
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(esc->sc_main_dmamap->dm_mapsize == 0) &&
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(esc->sc_tail_dmamap->dm_mapsize == 0)) {
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esp_dma_print(sc);
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panic("%s: No DMA requested!",sc->sc_dev.dv_xname);
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}
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#endif
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@ -851,7 +925,7 @@ esp_dmacb_completed(map, arg)
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struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg;
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struct esp_softc *esc = (struct esp_softc *)sc;
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DPRINTF(("esp dma completed\n"));
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DPRINTF(("%s: dma completed\n",sc->sc_dev.dv_xname));
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#ifdef DIAGNOSTIC
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if ((esc->sc_datain < 0) || (esc->sc_datain > 1)) {
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@ -878,7 +952,7 @@ esp_dmacb_shutdown(arg)
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struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg;
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struct esp_softc *esc = (struct esp_softc *)sc;
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DPRINTF(("esp dma shutdown\n"));
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DPRINTF(("%s: dma shutdown\n",sc->sc_dev.dv_xname));
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/* Stuff the end slop into fifo */
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@ -886,9 +960,11 @@ esp_dmacb_shutdown(arg)
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if (esp_debug) {
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int n = NCR_READ_REG(sc, NCR_FFLAG);
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DPRINTF(("esp fifo size = %d, seq = 0x%x\n",n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5));
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DPRINTF(("%s: fifo size = %d, seq = 0x%x\n",
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sc->sc_dev.dv_xname,n & NCRFIFO_FF, (n & NCRFIFO_SS)>>5));
|
||||
|
||||
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d\n",
|
||||
NCR_DMA(("%s:dmaintr: tcl=%d, tcm=%d, tch=%d\n",
|
||||
sc->sc_dev.dv_xname,
|
||||
NCR_READ_REG(sc, NCR_TCL),
|
||||
NCR_READ_REG(sc, NCR_TCM),
|
||||
(sc->sc_cfg2 & NCRCFG2_FE)
|
||||
@ -940,11 +1016,20 @@ esp_dmacb_shutdown(arg)
|
||||
esc->sc_datain = -1;
|
||||
esc->sc_dmaaddr = 0;
|
||||
esc->sc_dmalen = 0;
|
||||
esc->sc_dmasize = -1;
|
||||
esc->sc_dmasize = 0;
|
||||
|
||||
esc->sc_loaded = 0;
|
||||
|
||||
esc->sc_begin = 0;
|
||||
esc->sc_begin_size = 0;
|
||||
|
||||
#ifdef ESP_DEBUG
|
||||
if (esp_debug) {
|
||||
printf(" *intrstat = 0x%b\n",
|
||||
(*(volatile u_long *)IIOV(NEXT_P_INTRSTAT)),NEXT_INTR_BITS);
|
||||
printf(" *intrmask = 0x%b\n",
|
||||
(*(volatile u_long *)IIOV(NEXT_P_INTRMASK)),NEXT_INTR_BITS);
|
||||
}
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: espvar.h,v 1.8 1999/02/13 09:44:50 dbj Exp $ */
|
||||
/* $NetBSD: espvar.h,v 1.9 1999/02/14 10:19:51 dbj Exp $ */
|
||||
|
||||
/*-
|
||||
* Copyright (c) 1997 The NetBSD Foundation, Inc.
|
||||
@ -69,8 +69,8 @@ struct esp_softc {
|
||||
* buffer into a "tail" buffer that we can control more carefully.
|
||||
* We then chain this extra buffer onto the end.
|
||||
*/
|
||||
#define ESP_DMA_OVERRUN DMA_ENDALIGNMENT
|
||||
#define ESP_DMA_MAXTAIL 256
|
||||
#define ESP_DMA_OVERRUN 2*DMA_ENDALIGNMENT
|
||||
#define ESP_DMA_MAXTAIL 128
|
||||
#define ESP_DMA_TAILBUFSIZE (ESP_DMA_MAXTAIL+2*DMA_ENDALIGNMENT+ESP_DMA_OVERRUN)
|
||||
bus_dmamap_t sc_tail_dmamap;
|
||||
caddr_t sc_tail; /* pointer into sc_tailbuf, NULL if invalid */
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* $NetBSD: nextdma.c,v 1.11 1999/02/13 09:44:50 dbj Exp $ */
|
||||
/* $NetBSD: nextdma.c,v 1.12 1999/02/14 10:19:51 dbj Exp $ */
|
||||
/*
|
||||
* Copyright (c) 1998 Darrin B. Jewell
|
||||
* All rights reserved.
|
||||
@ -264,11 +264,13 @@ next_dma_rotate(nd)
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (nd->_nd_map_cont) {
|
||||
if (!DMA_BEGINALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_addr)) {
|
||||
if (!DMA_BEGINALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr)) {
|
||||
next_dma_print(nd);
|
||||
panic("DMA request unaligned at start\n");
|
||||
}
|
||||
if (!DMA_ENDALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_addr +
|
||||
nd->_nd_map_cont->dm_segs[nd->_nd_idx].ds_len)) {
|
||||
if (!DMA_ENDALIGNED(nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_addr +
|
||||
nd->_nd_map_cont->dm_segs[nd->_nd_idx_cont].ds_len)) {
|
||||
next_dma_print(nd);
|
||||
panic("DMA request unaligned at end\n");
|
||||
}
|
||||
}
|
||||
@ -418,6 +420,10 @@ next_dma_print(nd)
|
||||
dd_saved_start = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_START);
|
||||
dd_saved_stop = bus_space_read_4(nd->nd_bst, nd->nd_bsh, DD_SAVED_STOP);
|
||||
|
||||
/* NDMAP is Next DMA Print (really!) */
|
||||
|
||||
printf("NDMAP: nd->_nd_dmadir = 0x%08x\n",nd->_nd_dmadir);
|
||||
|
||||
if (nd->_nd_map) {
|
||||
printf("NDMAP: nd->_nd_map->dm_mapsize = %d\n",
|
||||
nd->_nd_map->dm_mapsize);
|
||||
@ -523,14 +529,7 @@ nextdma_intr(arg)
|
||||
if (!nd->_nd_map_cont) {
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
if (state & (DMACSR_SUPDATE|DMACSR_ENABLE)) {
|
||||
next_dma_print(nd);
|
||||
panic("unexpected bits set in DMA state at shutdown (0x%b)\n", state,DMACSR_BITS);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DIAGNOSTIC
|
||||
#if 0 /* Sometimes the DMA registers have totally bogus values when read.
|
||||
#if 1 /* Sometimes the DMA registers have totally bogus values when read.
|
||||
* Until that's understood, we skip this check
|
||||
*/
|
||||
|
||||
@ -559,6 +558,16 @@ nextdma_intr(arg)
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
#ifdef DIAGNOSTIC
|
||||
if (state & (DMACSR_SUPDATE|DMACSR_ENABLE)) {
|
||||
next_dma_print(nd);
|
||||
panic("DMA: unexpected bits set in DMA state at shutdown (0x%b)\n",
|
||||
state,DMACSR_BITS);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
if ((nd->_nd_idx+1) == nd->_nd_map->dm_nsegs) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user