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Minor cleanup.

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Make the initializer for BAUDLO depend on PCLK directly; it was incorrect on
some ports where PCLK is not 4.9152MHz.
XXX Is the default value actually used?
This commit is contained in:
mycroft 1999-02-11 15:28:03 +00:00
parent cd6ab900da
commit 2a304686e6
10 changed files with 50 additions and 48 deletions
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4
sys/arch/atari/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.29 1998/03/25 09:46:10 leo Exp $ */
/* $NetBSD: zs.c,v 1.30 1999/02/11 15:28:03 mycroft Exp $ */
/*
* Copyright (c) 1995 L. Weppelman (Atari modifications)
@ -82,7 +82,7 @@
#if NZS > 0
#define PCLK (8053976) /* PCLK pin input clock rate */
#define PCLK_HD (14745600) /* PCLK on Hades pin input clock rate */
#define PCLK_HD (9600 * 1536) /* PCLK on Hades pin input clock rate */
#define splzs spl5

23
sys/arch/mac68k/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.28 1999/02/03 20:25:06 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.29 1999/02/11 15:28:04 mycroft Exp $ */
/*
* Copyright (c) 1996-1998 Bill Studenmund
@ -82,7 +82,8 @@
/* Booter flags interface */
#define ZSMAC_RAW 0x01
#define ZSMAC_LOCALTALK 0x02
#define ZS_STD_BRG (57600*4)
#define PCLK (9600 * 384)
#include "zsc.h" /* get the # of zs chips defined */
@ -166,9 +167,9 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA,
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};
@ -297,7 +298,7 @@ zsc_attach(parent, self, aux)
bcopy(zs_init_reg, cs->cs_preg, 16);
/* Current BAUD rate generator clock. */
cs->cs_brg_clk = ZS_STD_BRG; /* RTxC is 230400*16, so use 230400 */
cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */
cs->cs_defspeed = zs_defspeed[zsc_unit][channel];
cs->cs_defcflag = zs_def_cflag;
@ -312,7 +313,7 @@ zsc_attach(parent, self, aux)
#endif
/* Define BAUD rate stuff. */
xcs->cs_clocks[0].clk = ZS_STD_BRG * 16;
xcs->cs_clocks[0].clk = PCLK;
xcs->cs_clocks[0].flags = ZSC_RTXBRG;
xcs->cs_clocks[1].flags =
ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN;
@ -541,10 +542,10 @@ zs_cn_check_speed(bps)
{
int tc, rate;
tc = BPS_TO_TCONST(ZS_STD_BRG, bps);
tc = BPS_TO_TCONST(PCLK / 16, bps);
if (tc < 0)
return 0;
rate = TCONST_TO_BPS(ZS_STD_BRG, tc);
rate = TCONST_TO_BPS(PCLK / 16, tc);
if (ZS_TOLERANCE > abs(((rate - bps)*1000)/bps))
return 1;
else
@ -658,7 +659,7 @@ zs_set_speed(cs, bps)
if (sf & ZSC_EXTERN)
cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;
else
cs->cs_brg_clk = ZS_STD_BRG;
cs->cs_brg_clk = PCLK / 16;
/*
* Now we have a source, so set it up.
@ -893,7 +894,7 @@ zscnsetup()
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
cs->cs_channel = zs_consunit;
cs->cs_brg_clk = ZS_STD_BRG;
cs->cs_brg_clk = PCLK / 16;
bcopy(zs_init_reg, cs->cs_preg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;

21
sys/arch/macppc/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.10 1999/02/03 20:25:06 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.11 1999/02/11 15:28:04 mycroft Exp $ */
/*
* Copyright (c) 1996, 1998 Bill Studenmund
@ -80,7 +80,8 @@
/* Booter flags interface */
#define ZSMAC_RAW 0x01
#define ZSMAC_LOCALTALK 0x02
#define ZS_STD_BRG (57600*4)
#define PCLK (9600 * 384)
#include "zsc.h" /* get the # of zs chips defined */
@ -156,9 +157,9 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
1, /*12: BAUDLO (default=38400) */
0, /*13: BAUDHI (default=38400) */
ZSWR14_BAUD_ENA,
((PCLK/32)/38400)-2, /*12: BAUDLO (default=38400) */
0, /*13: BAUDHI (default=38400) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};
@ -320,7 +321,7 @@ zsc_attach(parent, self, aux)
bcopy(zs_init_reg, cs->cs_preg, 16);
/* Current BAUD rate generator clock. */
cs->cs_brg_clk = ZS_STD_BRG; /* RTxC is 230400*16, so use 230400 */
cs->cs_brg_clk = PCLK / 16; /* RTxC is 230400*16, so use 230400 */
cs->cs_defspeed = zs_defspeed[zsc_unit][channel];
cs->cs_defcflag = zs_def_cflag;
@ -335,7 +336,7 @@ zsc_attach(parent, self, aux)
#endif
/* Define BAUD rate stuff. */
xcs->cs_clocks[0].clk = ZS_STD_BRG * 16;
xcs->cs_clocks[0].clk = PCLK;
xcs->cs_clocks[0].flags = ZSC_RTXBRG | ZSC_RTXDIV;
xcs->cs_clocks[1].flags =
ZSC_RTXBRG | ZSC_RTXDIV | ZSC_VARIABLE | ZSC_EXTERN;
@ -617,10 +618,10 @@ zs_cn_check_speed(bps)
{
int tc, rate;
tc = BPS_TO_TCONST(ZS_STD_BRG, bps);
tc = BPS_TO_TCONST(PCLK / 16, bps);
if (tc < 0)
return 0;
rate = TCONST_TO_BPS(ZS_STD_BRG, tc);
rate = TCONST_TO_BPS(PCLK / 16, tc);
if (ZS_TOLERANCE > abs(((rate - bps)*1000)/bps))
return 1;
else
@ -734,7 +735,7 @@ zs_set_speed(cs, bps)
if (sf & ZSC_EXTERN)
cs->cs_brg_clk = xcs->cs_clocks[i].clk >> 4;
else
cs->cs_brg_clk = ZS_STD_BRG;
cs->cs_brg_clk = PCLK / 16;
/*
* Now we have a source, so set it up.

6
sys/arch/mvme68k/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.16 1999/02/03 20:25:06 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.17 1999/02/11 15:28:04 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -103,8 +103,8 @@ u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};

8
sys/arch/newsmips/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.5 1999/02/03 20:25:06 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.6 1999/02/11 15:28:05 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -89,7 +89,7 @@ int zs_major = 1;
* The news3400 provides a 4.9152 MHz clock to the ZS chips.
*/
#define PCLK1 (9600 * 512) /* PCLK pin input clock rate */
#define PCLK2 (7200 * 512)
#define PCLK2 (9600 * 384)
/*
* Define interrupt levels.
@ -130,8 +130,8 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK1/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};

12
sys/arch/next68k/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.6 1999/02/03 20:25:06 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.7 1999/02/11 15:28:05 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -92,9 +92,9 @@ int zs_major = 12;
* The NeXT provides a 3.686400 MHz clock to the ZS chips.
*/
#if 1
#define PCLK (57600*4*16) /* PCLK pin input clock rate */
#define PCLK (9600 * 384) /* PCLK pin input clock rate */
#else
#define PCLK 10000000
#define PCLK 10000000
#endif
#define ZS_DELAY() delay(2)
@ -131,8 +131,8 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};
@ -695,7 +695,7 @@ zscninit(cn)
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
cs->cs_channel = zs_consunit;
cs->cs_brg_clk = PCLK/16;
cs->cs_brg_clk = PCLK / 16;
bcopy(zs_init_reg, cs->cs_preg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;

6
sys/arch/sparc/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.62 1999/02/03 20:25:06 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.63 1999/02/11 15:28:05 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -152,8 +152,8 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};

6
sys/arch/sparc64/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.6 1999/02/03 20:25:07 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.7 1999/02/11 15:28:05 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -153,8 +153,8 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE | ZSWR9_NO_VECTOR,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};

6
sys/arch/sun3/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.55 1999/02/03 20:25:07 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.56 1999/02/11 15:28:06 mycroft Exp $ */
/*-
* Copyright (c) 1996 The NetBSD Foundation, Inc.
@ -151,8 +151,8 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};

6
sys/arch/x68k/dev/zs.c
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@ -1,4 +1,4 @@
/* $NetBSD: zs.c,v 1.13 1999/02/03 20:25:07 mycroft Exp $ */
/* $NetBSD: zs.c,v 1.14 1999/02/11 15:28:06 mycroft Exp $ */
/*-
* Copyright (c) 1998 Minoura Makoto
@ -98,8 +98,8 @@ static u_char zs_init_reg[16] = {
ZSWR9_MASTER_IE,
ZSWR10_NRZ, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
((PCLK/32)/9600)-2, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};