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32900 Commits

Author SHA1 Message Date
matt
ffdea2c266 Only do the dssall if cpu_altivec is set. 2002-08-23 16:08:10 +00:00
scw
b3e086e0ce Attach the ECC driver instead of the previous "eccirq" property hack. 2002-08-23 15:03:33 +00:00
scw
5b79fdfaf7 Add "ecc at plb" device. 
Add an "irq" locator to the plb device.
This gets rid of the original hack where ecc support was wedged into
the cpu driver.
 2002-08-23 15:01:07 +00:00
simonb
3502025a54 Show the IRQ we attach the ECC handler to. 2002-08-23 13:43:18 +00:00
simonb
a9560f7ab2 Don't pass PROP_CONST to board_info_set() for variables that are on 
the stack; we want to copy the property into the database.
 2002-08-23 13:41:55 +00:00
scw
3a0067a42a Comment out wscons-related options until port-specific code is written. 2002-08-23 13:16:23 +00:00
scw
9ba60b4297 Install the ECC error interrupt handler at the level specified by 
a "4xx-ecc-irq" property.
If the property isn't defined, assume the hardware has no ECC support.
This should, ideally, be a config file option.
 2002-08-23 12:46:49 +00:00
scw
c4fdfebd38 Allow port-specific Makefiles to override the name and location 
of locore.[So].
This is in preparation for arch/evbppc.
 2002-08-23 12:01:58 +00:00
scw
a0d58bf2f5 Remove an extra trailing bracket in a DEBUG printf. 2002-08-23 11:59:40 +00:00
scw
f384fe8ba7 Don't assume all com ports run at "COM_FREQ", or a multiple thereof. 
Use a board-specific property instead.
 2002-08-23 11:42:13 +00:00
scw
19c988633d Don't frob cpu-specific DCR registers in common code. 2002-08-23 11:40:07 +00:00
scw
4968573654 Split off common 4xx locore code so it can be re-used by other 4xx ports. 2002-08-23 11:37:53 +00:00
thorpej
90817e313c Use the structures defined in bsd_openprom.h for "reg", "range", 
and "intr" properties, rather than having identical-except-for-names
sbus_* and iommu_* versions.
 2002-08-23 02:53:10 +00:00
thorpej
e92b96b3c4 CPU_ISSUN4OR4C -> CPU_ISSUN4 || CPU_ISSUN4C 2002-08-23 02:46:37 +00:00
thorpej
8b7cc1c1d2 Protect against multiple inclusion. 2002-08-23 02:45:44 +00:00
thorpej
de6a644cea * Refine the comment describing openprom_addr. 
* Add openprom_range and openprom_intr structures.
 2002-08-23 01:08:45 +00:00
wrstuden
e85eb3093d Enable memory for cards with 64-bit memory mappings in addition to 
32-bit memory mappings. Makes Intel GigE card work in my Beige G3.

Patch from thorpej
 2002-08-22 22:47:35 +00:00
matt
510b31be28 Add missing PMAPCOUNT2 macro for the non-PMAPCOUNTERS case 2002-08-22 15:43:08 +00:00
abs
2287052465 PIPE_SOCKETPAIR, MALLOC_NOINLINE and VNODE_OP_NOINLINE are all appropriate for 
the 'minimal memory' configurations.
 2002-08-22 14:36:48 +00:00
briggs
02aeef1d79 Handle copies to unaligned addresses a bit better. 2002-08-22 05:01:02 +00:00
thorpej
6cc7c1c1ff * Add PTE_SYNC() and PTE_SYNC_RANGE() macros. These don't actually do 
anything yet.
* Use PTE_SYNC() and PTE_SYNC_RANGE() in some obvious places, i.e.
  where vtopte() is used.
 2002-08-22 01:13:53 +00:00
thorpej
574a9cc019 Use a pool cache for PT-PTs. 2002-08-21 21:22:52 +00:00
matt
9e33535006 Add more evcnt entries for monitoring the page table entries. 2002-08-21 18:36:55 +00:00
thorpej
5fddbbe3d5 Do cached memory access to L1 tables, making sure to write-back the 
cache after any L1 table modifications.
 2002-08-21 18:34:31 +00:00
matt
c7a899fa13 Use "b" constraint for base registers (indexed addressing mode). 2002-08-20 06:04:38 +00:00
shin
b46ba8b021 don't include same file twice. 2002-08-20 04:22:03 +00:00
briggs
d2c9e5deb4 Disable coalesced writes on IOP310-based systems. 2002-08-20 02:34:04 +00:00
briggs
88452ee2b5 Coalesced writes on xscale systems do not always work. If 
XSCALE_NO_COALESCE_WRITES is set, disable.  Otherwise, enable.
 2002-08-20 02:30:51 +00:00
briggs
50e0ea7aa2 Enable branch prediction and write coalescing on XScale. 2002-08-20 02:00:46 +00:00
fredette
fa8a85a54d Cleaned up BTLB support. There are no longer BTLB function pointers 
in struct hppa_cpu_info or anywhere else, now there are just hppa_btlb_*
functions.  Added support for machines with split I/D and variable-range
BTLBs.  Added support for purging BTLB entries.
 2002-08-19 18:58:26 +00:00
fredette
0ebb2cb8a8 Since trap_kdebug() may be a macro, be sure to cast to void when not 
using its result.
 2002-08-19 15:07:33 +00:00
simonb
0702d44ac5 Fix printf format string for the EXTENT_DEBUG case. 2002-08-19 12:03:48 +00:00
simonb
771cbe3e84 Remove CPU_MIPS_DOUBLE_COUNT for the MIPS 20Kc - it's cycle counter runs 
at the normel CPU frequency.
 2002-08-19 12:03:04 +00:00
matt
8a75cdd09b Add evcnt's for common pmap activities when PMAPCOUNTERS is defined 
in the config file.
 2002-08-18 19:18:33 +00:00
matt
5ba45ecc9c defflag PMAPDEBUG, PMAPCHECK, and PMAPCOUNTERS into opt_pmap.h 2002-08-18 17:17:59 +00:00
simonb
7e0228bbc3 Update to rev 1.48 from Algorithmics; adds BONITO64 register definitions. 2002-08-18 16:00:33 +00:00
simonb
fd2320f396 Issue a dummy read after a write to the BONITO_PCIMAP_CFG register to 
make sure the write is posted; needed to keep the BONITO64 happy.
 2002-08-18 15:57:55 +00:00
briggs
d5135f0f8e We do not need HZ=512 here, for sure. 2002-08-18 04:12:42 +00:00
thorpej
a7d44c2503 Use separate function pointers for dmamap_sync pre- vs post- operations. 
Change the bus_dmamap_sync() macro to test the ops argument against pre-
and post- constants.  The compiler will optimize out dead code because
of the constants.  Since post- operations are not needed on ARM (except
for ISA bounce buffers), this eliminate a large number of function calls
which are noops, each of which cost at least 6 cycles just in the call
and return overhead (not to mention whatever other useless work the
compiler decides to do in the callee).
 2002-08-17 20:46:26 +00:00
briggs
c7ee5cd55e Compile properly without DIAGNOSTIC defined. 2002-08-17 19:19:57 +00:00
briggs
126f6cf9bc Add a new option EVBARM_BOARDTYPE to differentiate between different 
evbarm ports.  Inline _splraise/_spllower/splx for i80321 and iq80310
for more performance.
 2002-08-17 16:42:20 +00:00
thorpej
003b8e8bca More local label fixups. 2002-08-17 16:36:31 +00:00
briggs
20267a208f Do not trim 'offset' from 'len' in _bus_dmamap_sync_linear(). 2002-08-17 05:14:10 +00:00
thorpej
7cbd25232f Use correct-for-ELF local labels. 2002-08-17 03:14:47 +00:00
uwe
fdc57c1775 Add missing slash to /* notyet * 2002-08-17 02:23:18 +00:00
briggs
d86c947b8c Inline bus_dma_inrange() and bus_dmamap_sync_*(). 2002-08-17 01:15:15 +00:00
thorpej
50fe583069 Must ... micro ... optimize! 
* Save an instruction in the transition from idle to have-process-to-
  switch-to, and eliminate two instructions that cause datadep-stalls
  on StrongARM And XScale (one in each idle block).
* Rearrange some other instructions to avoid datadep-stalls on StrongARM
  and XScale.
* Since cpu_do_powersave == 0 is by far the common case, avoid a
  pipeline flush by reordering the two idle blocks.
 2002-08-17 01:08:21 +00:00
chris
1334ab7d1e following Jason's change to _xscale, convert bpl's to bhi's, saves looping more than needed in some cases. 2002-08-17 01:02:38 +00:00
bjh21
47226343a9 Be consistent about the type of idle(). 2002-08-17 00:01:23 +00:00
bjh21
72f31d9112 If we're treating the MEMC as a TLB, there's no need to completely reload 
it in pmap_activate().  Instead, let's leave it empty and let pages be
faulted into it on demand.  This improves the context switch latency
somewhat, at least for small processes.
 2002-08-16 22:51:43 +00:00
bjh21
4d7743ff17 According to Chuck Silvers, pmap_copy_page() and pmap_zero_page() don't 
need to mess with the referenced and modified flags, since they're only
called when a page is being initialised, and is about to have them cleared.
Make this so.
 2002-08-16 21:16:48 +00:00
thorpej
ebff575bc3 * Add a new machdep.powersave sysctl, which controls the use of 
the CPU's "sleep" function in the idle loop.
* Default all CPUs to not use powersave, except for the PDA processors
  (SA11x0 and PXA2x0).

This significantly reduces inteterrupt latency in high-performance
applications (and was good to squeeze another ~10% out of an XScale
IOP on a Gig-E benchmark).
 2002-08-16 15:25:53 +00:00
fredette
a3961f4a15 This cleans up interrupts with respect to GSC bus chips and the devices 
they contain.  IRQ information for these has been removed from the
kernel configuration file.  GSC bus chips now choose an available CPU
IRQ for themselves, and know IRQ information for all of the devices
they may contain.  Minor autoconfiguration changes support this.

Renamed the old-style vmstat interrupt counters to say "ipl" and not
"irq", since they've been disconnected from irq numbers.  Also provide
a function to allocate an irq bit from an interrupt register, and a
function to report the next ipl bit that will be allocated.
 2002-08-16 15:02:39 +00:00
petrov
4f9cdf2197 Enable sab. 2002-08-16 09:03:36 +00:00
petrov
560e50e242 Add sab. 2002-08-16 08:56:44 +00:00
msaitoh
3bc4d0b5aa remove extra CRLF conversion 2002-08-16 08:56:27 +00:00
petrov
e879a86b97 Add sab. 2002-08-16 08:52:48 +00:00
petrov
0e426c8d8b Port Jason L. Wright's sab82532 driver. From OpenBSD. 2002-08-16 08:47:13 +00:00
briggs
b84fadb38b i80200_extirq_dispatch takes a struct irqframe * now. 2002-08-16 04:55:48 +00:00
thorpej
cb80293b4b If __ARMEB__ is defined, always set CPU_CONTROL_BEND_ENABLE in 
the CPU control register.
 2002-08-16 00:06:26 +00:00
fredette
d02fd6e543 Fixed the match logic to only match one unit, and only for the 
(pseudo)module named "pdc".
 2002-08-15 04:22:02 +00:00
briggs
c0366588ce Use local label names (.Lfoo vs. (Lfoo or foo)) 2002-08-15 01:38:16 +00:00
briggs
fa81e3d75e * Use local label names (.Lfoo vs. (Lfoo or foo)) 
* When moving from cpsr, use "cpsr" instead of "cpsr_all" (which is
   provided, but doesn't make sense since mrs doesn't support fields
   like msr does).
 2002-08-15 01:37:01 +00:00
thorpej
45adf20cfe Whitespace. 2002-08-14 23:53:07 +00:00
thorpej
4706ae8670 Use cpsr_c rather then cpsr_all where appropriate. 2002-08-14 23:33:11 +00:00
thorpej
278ecc271f Fix some whitespace. 2002-08-14 23:30:21 +00:00
thorpej
323a5902ee Garbage-collect some unused routines. 2002-08-14 23:24:46 +00:00
thorpej
ad73349331 We only need to modify the CPSR's control field, so use cpsr_c rather 
than cpsr_all.
 2002-08-14 23:23:06 +00:00
chris
f4c605201d Tweak asm to avoid a couple of stalls. 2002-08-14 23:07:36 +00:00
thorpej
b45159bad0 When doing PREREAD sync operations, if the start and end addresses 
of the range are aligned to a cacheline boundary, when do a dcache-inv
operation, rather than a dcache-wbinv operation.

XXX It could be a little smarter (align using wbinv, inv, then finish
up using wbinv), but even this simple change is good for a nearly 40%
improvement in my test case on XScale.
 2002-08-14 22:56:55 +00:00
thorpej
8df22142b8 Fix a fencepost in the cache flush routines, caused by using the wrong 
condition on a branch (bpl where bhi should have been used).  The error
caused one more line than intended to be flushed, which is particularly
bad if you're doing a dcache-invalidate operation.
 2002-08-14 22:53:19 +00:00
briggs
4bb5ae3d09 Inline SetCPSR calls where it seems prudent to do so. This avoids two 
branches and allows the compiler to better utilize registers around
calls to disable/enable/restore_interrupts().
 2002-08-14 21:55:52 +00:00
briggs
a957deca48 G/c cowfault. 2002-08-14 21:52:36 +00:00
thorpej
203dd6b325 * Add an ARM32_DMAMAP_COHERENT flag to indicate that a loaded DMA 
map contains "coherent" (non-cached in ARM-land) mappings.
* Set ARM32_DMAMAP_COHERENT in the map at the start of a load operation,
  and clear it in _bus_dmamap_load_buffer() if we encounter any cacheable
  mappings.
* In _bus_dmamap_sync(), if the map is marked COHERENT, skip any cache
  flushing.
 2002-08-14 20:50:37 +00:00
thorpej
eeebe88acf Don't need to frob CPSR in _splraise(). 2002-08-14 19:47:18 +00:00
thorpej
d00a4a068d Whe making a mapping "coherent", clear *ALL* the cache bits, not 
just L2_B and L2_C.
 2002-08-14 19:21:50 +00:00
kent
7ca0df5196 Fix incorrect ## usage. 2002-08-14 17:02:07 +00:00
fredette
670f0a07d9 First pass at changing how spl masks are built. Now there is no 
longer a forced correspondence between bit numbers in an interrupt
register and bit numbers in an spl mask.  This will avoid conflicts
between various interrupt registers in the same system.

Instead, bits in the spl mask are allocated on a first come, first
served basis by devices which can interrupt.  The new hp700_intr_ipending_new
takes care of reading all interrupt request registers that need
servicing, and mapping the bits set in those registers to new bits
set in ipending.

This whole mechanism is in and works.  A later commit will see the
I/O subsystems fixing which bits in their interrupt registers are
connected to which devices, largely removing irq information from
kernel configuration files.  There will also be a cosmetic fix to
show which spl bit corresponds to a device.
 2002-08-14 16:18:11 +00:00
matt
d2965f3ad3 Prepare for PPC64. Use register_t for mtmsr/mfmsr since the msr on PPC64 
is 64bits wide.  Define proper types for PPC64 if _LP64 is defined.
 2002-08-14 15:41:57 +00:00
matt
571dd402e2 Add a bunch of mpc8xx SPR definitions. 2002-08-14 15:38:40 +00:00
thorpej
201e41fc31 * Rename "word" -> 16, and "long" -> 32, as suggested by Ben Harris. 
* Replace __byte_swap_32_variable() with a C version from Richard
  Earnshaw that generates nearly identical assembly (and it would be
  exactly identical with the addition of another peephole to GCC ARM
  back-end).
 2002-08-14 15:08:57 +00:00
uwe
e7bdddc025 Fix botch in previous. #ifdef DIAGNOSTIC was one instructions too early 
in sparc_interrupt4m, thus breaking soft interrupts for normal 4m's.

Should fix port-sparc/17891 (thanks, Martin).
 2002-08-14 14:45:37 +00:00
matt
7f8f67eaed Re-enable PTE_EXEC. PTE_EXEC is now also cleared in pmap_zero_page, 
pmap_copy_page, and pmap_clear_modify (pmap_clear_bit).  Remove #ifdef
MULTIPROCESSOR since the cache instructions operate on all caches on
all processors.
 2002-08-14 14:25:15 +00:00
aymeric
c8bc51526f Remove the key repeating feature. 
It is asking for trouble and is useless for the X server.
We can add it back later if need be.
 2002-08-14 13:02:58 +00:00
shin
f14283b93c .cvsignore should not be used. 2002-08-14 12:44:33 +00:00
simonb
bff11b16da Remove the "comfound < 2" bogosity. 2002-08-14 12:31:38 +00:00
simonb
2eded71179 Remove an unused global variable (that was marked with an XXX!). 2002-08-14 12:29:50 +00:00
thorpej
da5ef20b1a Byte-swapping optimizations, enabled if compiling with GCC: 
* Byte-swap 16-bit and 32-bit constants at compile-time.
* Inline 16-bit and 32-bit variable byte-swaps.  These take 3 and 4
  insns, respectively, and inlining saves the minimum 6 cycle penalty
  to call/return from the byte swap function.
 2002-08-13 22:41:36 +00:00
fredette
0e92be5ea7 Converted the fault handlers for the PA7100LC and up to handle 
mappings not marked TLB_NO_RW_ALIAS.
 2002-08-13 20:29:52 +00:00
leo
0ec1f59ab6 For some reason, things stopped working without explicitely adding a rule 
to link the bootblocks... Found and fix provided by Thomas Gerner.
 2002-08-13 20:06:32 +00:00
aymeric
bb022a80b7 add (commented out) option WSDISPLAY_COMPAT_RAWKBD 2002-08-13 15:03:30 +00:00
aymeric
9e10bd8738 akbd's now have a raw mode, and implement the WSKBDIO_SETMODE ioctl. 
Adapted from OpenBSD.
 2002-08-13 15:00:42 +00:00
manu
5bd5c7bca2 Guard a variable declaration by #if so that it is not declared if it is not 
used.
 2002-08-13 09:46:21 +00:00
simonb
2f766ff3c2 Use the base space tag from the attach args, don't recreate it all the 
time.
Clean up some include files.
 2002-08-13 06:15:15 +00:00
simonb
b60f6d979d Remove old debugging printf(). 2002-08-13 05:52:11 +00:00
simonb
f0302072f1 Use "ibm4xx" instead of "galaxy"; galaxy was an early code name for the 
405GP.
 2002-08-13 05:43:24 +00:00
itojun
fe3d104e60 minor KNF 2002-08-13 05:33:51 +00:00
simonb
42dede3769 Move 4xx devices to their own config include file so they can be used 
elsewhere.
 2002-08-13 05:29:25 +00:00
simonb
9e00d2d7f9 Fix include file location botch in previous. 2002-08-13 05:25:39 +00:00
simonb
88682188fb Use the correct <foo>_attach_args; spotted by Jason Thorpe. 2002-08-13 05:23:33 +00:00
petrov
e36bdc8829 cpu_fork: clear PSTATE_PEF for a child process, reviewed by thorpej 2002-08-13 05:08:19 +00:00
simonb
497d6762cf Split out device register definitions to their own files as the are 
common across many of the 4xx parts.  Leaves ibm405gp.h with device
address information specific to the 405GP CPU.  Now allows opb.c to
support multiple 4xx CPU types.
 2002-08-13 04:57:48 +00:00
thorpej
98d6ec0b89 Add the brutal hack that allows us to limp along using the read/write 
cache line allocation policy on XScale CPUs: in pmap_enter(), if the
pmap is the kernel pmap, clear the X-bit in the PTE, thus disabling
read/write-allocate for managed kernel mappings.

Yes, this is ugly.  But it makes userland code run with r/w-allocate,
which is a huge improvement on systems with low core memory performance.
 2002-08-13 03:36:30 +00:00
thorpej
17c9690153 The Elan SC520's PIT runs at 1.1892MHz; set TIMER_FREQ so that 
time is kept properly.
 2002-08-13 02:46:36 +00:00
thorpej
65e781f38c Fix previous (need to add IO_TIMER1 to the register offsets). 2002-08-13 02:42:54 +00:00
itojun
f9b8434a5c fix includes (use dev/ic/i8253reg.h) 2002-08-13 02:17:45 +00:00
simonb
c34bffaed6 Add the `pci' device. 2002-08-13 01:15:31 +00:00
thorpej
05210534c0 No need for two copies of the i8253 register definitions. Remove the 
i386-specific copy, and adjust its users to add in the timer i/o base
as necessary.
 2002-08-13 00:50:33 +00:00
matt
c75c0aa911 Print DAR and DSISR on user ALIgnment traps (e.g. treat them as being 
similar to DSI tracks).
 2002-08-12 22:44:03 +00:00
rjs
92f063ee47 Always clear SA11x0 GPIO in interrupt handler. 2002-08-12 22:26:41 +00:00
thorpej
d7be866fc8 Rearrange the beginning of cpu_switch() slightly to reduce data-dep 
stalls on StrongARM and XScale.
 2002-08-12 21:00:12 +00:00
bjh21
28b7728edf Add RCSID and remove unused <sys/errno.h>. 2002-08-12 20:38:06 +00:00
bjh21
7c599c85ae Add RCSID. 2002-08-12 20:37:31 +00:00
bjh21
2e026f9f8c When copyin/out or copyin/outstr catches a pagefault, have it return the 
correct error code (provided by the fault handler in R0) rather than always
returning EFAULT.
 2002-08-12 20:34:47 +00:00
bjh21
664bea62e3 __KERNEL_RCSID 2002-08-12 20:19:04 +00:00
bjh21
ca86069053 When pcb_onfault is set, pass the error code we get from uvm_fault() 
(or EFAULT if we never called uvm_fault) to the onfault handler in R0,
in case it wants to use it.
 2002-08-12 20:17:37 +00:00
thorpej
3d6f9f69ab Make a slight tweak to register usage to save an instruction. 2002-08-12 19:33:01 +00:00
thorpej
4b8b317d4b There are other systems besides the PS/2 L40 that enable A20 
via the Configuration Port, so restructure the code a little
to allow for them, and list at least one other system that does
(anything based on AMD Elan SC520).

XXX We don't actually check for Elan SC520 yet.
 2002-08-12 14:27:34 +00:00
bjh21
596763b7de The only caller of fuswintr() and suswintr(), addupc_intr(), can handle their 
returning -1, so have them always do that rather than panicking.
 2002-08-12 14:20:44 +00:00
mrg
828c2ebb9f general clean up. should not affect anything. (this is part of a patch 
from eeh to reduce frivolous cache flushes.)
 2002-08-12 12:04:31 +00:00
simonb
b16f7fe1fc Add a pvr field to 'struct opb_dev', to allow the opb_devs array to 
contain info about on-chip devices for more than one CPU type.
 2002-08-12 07:55:08 +00:00
thorpej
156a4a378d Add elansc* at pci? (AMD Elan SC520 System Controller). 2002-08-12 03:28:52 +00:00
simonb
6bf1aaf8eb Reorganise the IBM 4xx bus layout, using terminology from the IBM 
documentation:
 - Remove "mainbus" altogether.
 - The new root is "plb" - the Processor Local Bus.
 - Attached to this is the "opb" - the On-chip Peripheral Bus, to which
   all the on-chip devices are attached (except the cpu and pci host
   bridge).
 - Port-specific code can pass an array of 'struct plb_dev' to
   config_rootfound() to attach extra devices to the plb.  The walnut
   port attaches a "pbus" (Peripheral Bus) in here for the RTC and
   pc keyboard controller to attach to.
There is still much 405GP specific code; the next round of changes will
generalise this to enable easier support for other 4xx CPUs.
 2002-08-12 02:06:18 +00:00
thorpej
7d2b11a8b0 Add a driver for the AMD Elan SC520 System Controller. The "elansc" 
driver attaches where "pchb" would normally attach (it matches at a
higher match priority).  The "elansc" driver currently provides support
for the watchdog timer built-in the SC520.

Thanks to Jasper Wallace for laying the ground-work for this (most
notably by providing a work-around for a watchdog-related bug in the
SC520).
 2002-08-12 01:03:12 +00:00
bjh21
657216ff0f Remove a file which was accidentally resurrected. 2002-08-11 23:20:11 +00:00
bjh21
206c97ccc2 Move the arm32 copystr.S from arch/arm/arm32 to arch/arm/arm and add support 
for 26-bit modes (basically saving R14 when we might get a page fault).
Use it on all ARM architectures now.
 2002-08-11 23:17:24 +00:00
fredette
02f0a2cf44 Significant pmap changes to no longer rely on the "U-bit" (TLB_UNCACHEABLE) 
to deal with aliasing of regular memory pages, because many processors don't
support it.

Now, the pmap marks all mappings of a page that has any non-equivalent
aliasing and any writable mapping, and the fault handlers watch for this
and flush other mappings out of the TLB and cache before (re)entering a
conflicting mapping.

When a page has non-equivalent aliasing, only one writable mapping at
a time may be in the TLB and cache.  If no writable mapping is in the
TLB and cache, any number of read-only mappings may be.

The PA7100LC/PA7300LC fault handlers have not been converted yet.
 2002-08-11 22:29:07 +00:00
bjh21
b6228a7d06 New, improved version of copyin(), copyout(), and kcopy() by Allen Briggs. 
This version works on both 26-bit and 32-bit machines.  For large copies,
it's up to three times as fast as the old arm32 version and five times as
fast as the old arm26 version.  For small copies it seems to be even faster
(getrusage() is apparently over ten times faster on an ARM610).

Hooray for Allen!
 2002-08-11 21:19:12 +00:00
bjh21
cf963eaeb7 Add a curpcb variable, since the new bcopyinout.S will need one. 2002-08-11 20:50:39 +00:00
bjh21
947a208541 Disable IRQs and FIQs when rebooting. 2002-08-11 20:45:10 +00:00
bjh21
bd0fd7fdb4 BUFPAGES=2 seems to be the practical minimum. 2002-08-11 20:43:51 +00:00
fredette
2e5e562514 Add better support for controlling the LEDs, and use it. Now the 
LEDs blink on network receive, network send, and disk interrupt,
and the high LEDs display the current load average (up to 15).
 2002-08-11 19:53:41 +00:00
fredette
960ef7a15a Made changes to how bus_dmamap_sync() and the if_ie_gsc driver work 
when it comes to flushing the cache.  These changes should eliminate
the "ie0: receive descriptors out of sync" and "ie0: reset" messages.
 2002-08-11 19:39:37 +00:00
fredette
68e5ca694d Undo the previous change. Polling the console any slower makes 
the console unusable.
 2002-08-11 19:17:45 +00:00
itojun
951e585780 probe/attach Dell TrueMobile 1150 MiniPCI 802.11b card - not very useful 
without external antenna...

cbb0: interruptingaat irq 10
cardslot0 at cbb0 slot 0 flags 0
cardbus0 at cardslot0: bus 1 device 0
pcmcia0 at cardslot0
wi0 at pcmcia0 function 0: Dell, TrueMobile 1150 Series PC Card, Version 01.01
wi0: 802.11 address 00:02:2d:6c:db:f6
wi0: using Lucent Embedded WaveLAN/IEEE
wi0: Lucent Firmware: Station (8.10.1)
wi0: supported rates: 1Mbps, 2Mbps, 5.5Mbps, 11Mbps
 2002-08-11 16:22:09 +00:00
isaki
b9015555de Commented out slhci. it's experimental yet. 2002-08-11 13:50:45 +00:00
simonb
95319edf4a Add some IBM 4xx CPU PVR values; sort PVRs numerically. 
White space nits.
 2002-08-11 13:33:00 +00:00
simonb
ef1df3654e Define the 4xx PVR values in one place only. 2002-08-11 13:32:20 +00:00
isaki
8bf06813d7 Add slhci0, ScanLogic SL811HS/T USB Host Contoller. 2002-08-11 13:26:28 +00:00
isaki
6746f40ce5 Add usb*, ugen* 2002-08-11 13:21:07 +00:00
isaki
0b6db80ce5 Add ScanLogic SL811HS/T USB Host Controller and USB stuff. 2002-08-11 13:19:35 +00:00
isaki
b553867e0d Add (commented) ScanLogic SL811HS/T USB Host Controller 
and USB stuff.
 2002-08-11 13:18:57 +00:00
isaki
dd0e0396bc Add driver for ScanLogic SL811HS/T USB Host Controller. 
XXX It's experimental code yet.

For x68k: USB part of Nereid USB/Ethernet/memory board
For ISA:  ISA USB Host board from Morphy planning
 2002-08-11 13:17:52 +00:00
matt
dcab4f46e8 Switch back to kenter_pa/kremove 2002-08-11 02:17:30 +00:00
hannken
f6391479b2 Convert to new device buffer queue interface. 
Approved by: Leo Weppelman <leo@netbsd.org>
 2002-08-10 21:49:14 +00:00
matt
549ac19770 Add IBM Power3 CPUID. 2002-08-10 21:38:06 +00:00
thorpej
3721870c9e Add wi* at pci? 2002-08-10 20:20:22 +00:00
matt
67f40b1907 More refinement, only map B_READ buf with VM_PROT_WRITE (all pages always 
have VM_PROT_READ).  Also, pass PMAP_WIRED to pmap_enter (for non-mpc6xx
pmaps).  This will give pmap clues about flushing any "icache ok state".
 2002-08-10 18:49:56 +00:00
matt
246ee3ef1d Switch vmap*buf back to using pmap_enter/pmap_remove. This is so that 
accesses to the buffer will cause the reference and modified bits for
the pages to be udpated appropriately.
 2002-08-10 16:28:49 +00:00
minoura
013897f2cc Add quirk for Connectix Virtual PC 5 (for Windows at least) emulated 
PCI bridge (440BX).
Note that there's still a problem that emulated 21140 cannot be driven
by if_tlp.  Workaround is to use if_de.
 2002-08-10 03:37:40 +00:00
thorpej
76730bd0cc Tidy up pmap_clean_page() a little, and reenable some code that was 
disabled previously: Skip cleaning mappings which are read-only, because
the pmap (now) does clean pages on a r/w -> r/o transition.
 2002-08-10 00:48:35 +00:00
thorpej
006a578742 Clean up some warts in pmap_protect(). 2002-08-10 00:11:51 +00:00
thorpej
15a5e8f238 cpu_fork(): If PMCs are not enabled in the parent, clear the machine- 
dependent PMC state in the child.
 2002-08-09 23:44:17 +00:00
thorpej
19227e620e Add a PVF_EXEC -- we don't use it yet, though. 2002-08-09 23:08:39 +00:00
thorpej
6072e74ac1 * Drain write buffer after cleaning the mini-D$. 
* Fix a typo in a comment.
 2002-08-09 21:51:52 +00:00
thorpej
6ce0a206cc Add an XSCALE_CACHE_READ_WRITE_ALLOCATE option for people who 
want to play fast-and-loose.
 2002-08-09 21:49:09 +00:00
thorpej
884bc64586 Add some code, conditional on PMAP_ALIAS_DEBUG, that can be used to 
hunt for virtual aliases between managed (pmap_enter) and non-managed
(pmap_kenter_pa) mappings.
 2002-08-09 18:22:59 +00:00
tsutsui
1031f6caa4 Fix cacheinfo.c_nlines for sun4 and sun4c machines. 
(they are not used anyway..)
 2002-08-09 14:46:04 +00:00
simonb
5b415a20e5 Fix for when EMAC_EVENT_COUNTERS isn't defined. Problem reported by 
Allen Briggs.
 2002-08-09 14:10:30 +00:00
soren
642c31b4a3 Remove extraneous \n's in {err,warn}{,x}. 2002-08-09 10:01:53 +00:00
thorpej
c979315325 Reduce stalls on StrongARM and XScale by waiting one insn before using 
the result of a load.
 2002-08-09 06:18:24 +00:00
thorpej
afe3274eed Use ldrbt/strbt. Some other random cleanup. 2002-08-09 06:03:02 +00:00
thorpej
7d9de8b2ad PMC_TYPE_I586 -> PMC_CLASS_I586 
PMC_TYPE_I686 -> PMC_CLASS_I686
PMC_TYPE_K7 -> PMC_CLASS_K7

To reflect terminilogy used in pmc(3).
 2002-08-09 05:28:08 +00:00
thorpej
0291ab61ec * PMC_TYPE_I80200 -> PMC_CLASS_I80200 to reflect the terminology 
used in pmc(3).
* Some minor namespace cleanup.
 2002-08-09 05:27:09 +00:00
gmcgarry
91b47fddbb Garbage-collect cpu_sysctl(). From Shin'ichiro TAYA in PR-17888. 2002-08-09 05:10:45 +00:00
simonb
acce3a5e36 Add a driver the for IBM 405gp (and possibly other IBM 4xx cpus) ethernet 
MAC (emac).  Much thanks to Jason Thorpe for debugging help writing this
driver.  Tested on the walnut, and an earlier version of this driver works
on the OpenBlockSS.
 2002-08-09 04:17:26 +00:00
thorpej
410785d6f0 Use ldrt/strt. 2002-08-09 04:13:20 +00:00
matt
0fb9cba190 Add SPR_ASR from OEA-64. Change mfspr to use register_t. 2002-08-08 22:49:09 +00:00
thorpej
7cbc5d60c1 Add macros to encode the "unit number" in the event selector. 2002-08-08 20:40:49 +00:00
thorpej
b12f663377 Define new-style PMC types for i586, i686, and K7 performance counters. 2002-08-08 18:37:39 +00:00
briggs
5da3a2950b When configuring a counter, do not assume that it's not been configured in 
this process (mask off the register field before setting it).
 2002-08-08 18:23:46 +00:00
chs
0a97a311e2 it's PPC_HAVE_FPU, not PPC_HAS_FPU. 
also, include the headers that turn on FPU and AltiVec features
in case no one else does.
 2002-08-08 01:27:35 +00:00
ad
ac3f848ebe Replace FONT_LUCIDA with FONT_GALLANT. 2002-08-08 00:11:52 +00:00
thorpej
f91adb85ce * XSCALE_PMC_TYPE_I80200 -> PMC_TYPE_I80200 
* XSCALE_PMC_TYPE_CCNT -> PMC_TYPE_I80200_CCNT
* XSCALE_PMC_TYPE_PMCx -> PMC_TYPE_I80200_PMCx

Per discussion with Allen Briggs.
 2002-08-07 21:11:35 +00:00
matt
e66a17771e Disable PTE_EXEC optimization until I figure out why it fails on 750 but 
not 74xx.
 2002-08-07 19:04:05 +00:00
thorpej
fdcc8560e4 Speed up bcopy_page() on the XScale slightly by using the "pld" 
insn (prefetch) to look-ahead to the next chunk while we copy the
current chunk.

This could probably use a bit more tuning.
 2002-08-07 16:21:29 +00:00
bjh21
a0549f1aba Remove comment claiming that csc(4) doesn't work. 2002-08-07 14:42:42 +00:00
bjh21
d057306739 Enable csc(4), since it seems to be working now. 2002-08-07 13:40:26 +00:00
tron
38b5f64780 Redo last change. "pmc_evid_t" and "pmc_ctr_t" need to be visible for 
userland because they are used in "sys/pmc.h".
 2002-08-07 09:45:49 +00:00
tron
b145a3fa59 Embed "pmc_evid_t" and "pmc_ctr_t" into "if defined(_KERNEL)" and use 
"__uint64_t" from "int_types.h". This fixes "lint" errors while
building "libc".
 2002-08-07 09:34:54 +00:00
tsubai
e373d8b520 Re-correct previous. It's intentional. 2002-08-07 08:01:57 +00:00
hannken
bf7cb35ffa Convert to new device buffer queue interface. 
Approved by: Ignatios Souvatzis <is@netbsd.org>
 2002-08-07 07:29:13 +00:00
gmcgarry
21c1adacf3 Make file compile: 
- garbage collect cpu_sysctl()
- fix pasto
- include uvm/uvm_extern.h
From FUKAUMI Naoki in PR 17850.
 2002-08-07 07:21:08 +00:00
briggs
64a993291d Stubs for new pmc(9) interface. 2002-08-07 05:58:01 +00:00
chs
c86bd63e8e for ofb_enable_cache, turn on the BAT_M bit as well to prevent 
the framebuffer from getting scrambled on MP systems.
 2002-08-07 05:46:13 +00:00
briggs
d3cfa7ad3b Forward declare structures that are used here. 2002-08-07 05:38:47 +00:00
briggs
a27fd9df4d define pmc_evid_t, pmc_ctr_t. 2002-08-07 05:38:24 +00:00
chs
f65cb7133e mftb() has moved to cpu.h. 2002-08-07 05:20:46 +00:00
briggs
ba45c803fd PERFCTRS is now defflagged in conf/files. 2002-08-07 05:18:21 +00:00
briggs
0b956d0b8b Implement pmc(9) -- An interface to hardware performance monitoring 
counters.  These counters do not exist on all CPUs, but where they
do exist, can be used for counting events such as dcache misses that
would otherwise be difficult or impossible to instrument by code
inspection or hardware simulation.

pmc(9) is meant to be a general interface.  Initially, the Intel XScale
counters are the only ones supported.
 2002-08-07 05:14:47 +00:00
thorpej
c67cc2a5b8 Add iopaau, swdmover (commented out), and dmoverio. 2002-08-07 03:41:43 +00:00
thorpej
d6003ab996 Use -mcpu=xscale. 2002-08-07 03:40:01 +00:00
matt
a2e9fe106d Correct __va_list typedef for GCC 3.* to match the GCC 3.* definition. 2002-08-07 00:11:59 +00:00
itojun
8e7a88a3ff integer overflow. from silvio@qualys.com 2002-08-06 22:51:45 +00:00
itojun
e5b5171ab5 integer overflow. from silvio@qualys.com 2002-08-06 22:46:11 +00:00
itojun
05d221783a integer overflow. reported by silvio@qualys.com 2002-08-06 22:44:38 +00:00
thorpej
26bc8b27f4 - pmap_remove(): unmap the PTEs *after* we have finished with the 
page tables.
- pmap_enter(): if making a mapping for the same PA rw->ro, write-back
  the cache before doing so.
- pmap_clearbit(): if revoking REF on a page, make sure to wbinv the
  cache if the page has write permission, else inv the cache if the page's
  PTE is valid (XXX we actually wbinv in this case, as well, due to lack
  of idcache_inv_range()).  Only flush the TLB if the PTE changed.
 2002-08-06 21:43:51 +00:00
thorpej
0886c8cc0f Rearrange the exit path so that we don't do a idcache_wbinv_all *twice* 
when a process exits.
 2002-08-06 19:20:29 +00:00
thorpej
62d83d05b1 * Pass proc0 to switch_exit(), to make this a little more like the 
nathanw_sa branch.
* In switch_exit(), set the outgoing-proc register to NULL (rather than
  proc0) so that we actually use the "exiting process" optimization in
  cpu_switch().
 2002-08-06 17:44:35 +00:00
hannken
80fb19da39 Convert to new device buffer queue interface. 
Approved by: Paul Kranenburg <pk@netbsd.org>
 2002-08-06 14:44:15 +00:00
grant
3273a7757a add X note comment for INSECURE option. 
addresses port-i386/17853 from hclsmith@yahoo.ca.
 2002-08-06 12:09:42 +00:00
shin
b0d22e8404 fix CPU_ROOT_DEVICE implementation. 2002-08-06 06:54:36 +00:00
shin
d4552e01aa compilation fix. 2002-08-06 06:52:49 +00:00
chs
d3c3fef89b add code from tsubai to handle the second CPU on openpic machines. 
the second CPU on dual G4 boxes works now.
while I'm here, use mfmsr() and mtmsr() instead of inline asms.
 2002-08-06 06:26:19 +00:00
chs
f7fb853264 be sure to re-enable interrupts before calling trap() a second time 
due to an AST.  the rule is that we must always have interrupts
enabled when acquiring kernel_lock, so that we can process blocking IPIs
from another CPU which is already holding kernel_lock.
reduce differences between the MP and non-MP versions of this file.
 2002-08-06 06:21:58 +00:00
chs
f73abf90fb on MP systems, if the firmware didn't configure the L2 cache 
on the non-boot CPUs, copy the L2CR configuration from the boot CPU.
also, fix the code that configures the L2 cache so that it works at all.
while I'm here, use mfspr() and mtspr() instead of inline asms.
 2002-08-06 06:20:08 +00:00
chs
2928d8ba05 actually we shouldn't hold kernel_lock while calling postsig(). 2002-08-06 06:18:24 +00:00
chs
0924752f24 add the MSSCR0 register and some more L2CR fields. 2002-08-06 06:17:50 +00:00
chs
461184c6b6 fix the calculation of the address of the IPI dispatch register. 2002-08-06 06:16:42 +00:00
chs
ef0d8145a7 avoid races in mp_save_{fpu,vec}_proc() where the other CPU 
dumps the state out from under us.
 2002-08-06 06:16:04 +00:00
chs
301f1ebf31 move more inlines to cpu.h: mftb(), mftbl() and mfpvr(). 
(the mftb() in pmap.c only wanted the lower 32 bits, so that's now mftbl()).
 2002-08-06 06:14:33 +00:00
bjh21
a69295fb3b Enable csc(4), since it's reported as working. 2002-08-05 23:30:44 +00:00
bjh21
ed8346a525 Rather than forcing on XS_POLL in SCSI transfers ourselves, set 
SCSIPI_ADAPT_POLL_ONLY to tell the MI scsipi layer to do it for us.  This,
plus G/Cing some debugging code, removes the card-specific scsi_request
wrappers.
 2002-08-05 23:30:04 +00:00
fredette
16cf89e5a5 Made changes in where/how the kernel is linked, and how the pmap 
maps it with BTLB entries, to minimize the number of BTLB entries
needed.

Because the CPU type was often guessed incorrectly, the mapping of
HP board number to system name now includes information about the
expected CPU type.
 2002-08-05 20:58:35 +00:00
fredette
190541e99d Poll the PDC console less frequently. 2002-08-05 20:38:35 +00:00
fredette
3295720e1a Don't use ldcw, since netisr might not be 16-byte aligned. 
Instead, disable interrupts and do a load and a store.
 2002-08-05 20:23:56 +00:00
shin
a59d490375 * add CPU_MIPS_NO_LLSC to Toshiba TX3912, TX3922, TX3927. 
* fix mips_has_llsc calculation logic.
 2002-08-05 13:02:40 +00:00
shin
2f33f11745 ++CPU_MAXID for CPU_LLSC. 2002-08-05 13:00:47 +00:00
enami
a55bfb4d51 A cosmetic change. 2002-08-05 02:56:58 +00:00
enami
1aaddc3669 - Care about carry bit when adding short value to force 4 byte boundary. 
It may contain any 32 bit value there.
- Use correct instruction to clear carry bit.
- Don't use series of load with update instruction.  It's slower.
 2002-08-05 02:55:39 +00:00
simonb
f068458085 The TX79 core in the R5900 doesn't support LL/SC. 
XXX: Others in this table will need to be updated.
 2002-08-05 02:18:43 +00:00
simonb
fef76c7e26 Use a __HAVE_BOOTINFO_H define to check for bootinfo support instead of 
speading port names in arch-dependant code.
 2002-08-05 02:13:14 +00:00
simonb
bf71dff7b9 Convert to use merged mips cpu_sysctl(). 2002-08-05 01:33:36 +00:00
itojun
dc8b2582ca backout previous 2002-08-05 01:16:59 +00:00
simonb
d67404d97e Fix tyop. 2002-08-05 01:15:22 +00:00
itojun
08a994ac23 soekris device use 19200bps on boot, it seems 2002-08-05 01:14:58 +00:00
thorpej
22e32aa941 #if 0 the stray interrupt messages -- we tend to get them "a lot" 
during normal activity on some IOP310-based designs.
 2002-08-04 17:52:46 +00:00
uwe
5b89d2589b In DIAGNOSTIC kernels detect situation that on sun4m neither hardware 
nor software interrupt pending bit is set for the current ipl.  Report
this as a "bogus" interrupt (better name anyone?).  This is a symptom
of a bug in interrupt handling in one of device drivers interrupting
at this ipl.  Reviewed by pk.
 2002-08-04 14:57:34 +00:00
simonb
6fbeccd902 Make this compile for the non-sbmips case. 2002-08-04 14:42:56 +00:00
isaki
2997fb2d61 Fix printf format in DIAGNOSTIC. 2002-08-04 13:08:29 +00:00
gmcgarry
460c8c3adc mipsco and sgimips also implement bootinfo, but didn't provide 
the CPU_BOOTED_KERNEL sysctl variable.
 2002-08-04 03:16:19 +00:00
gmcgarry
7470337484 Move LLSC feature test for mips1 to cputab[]. 2002-08-04 02:27:51 +00:00
thorpej
0aa15bdf33 Add support for "xor5", "xor6", "xor7", and "xor8". 2002-08-04 02:26:18 +00:00
gmcgarry
617f58fb55 Add sysctl variable to represent native CPU support for LL/SC instructions. 2002-08-04 01:47:15 +00:00
gmcgarry
886e32d355 mips1 doesn't have native LL/SC instructions. 2002-08-04 01:43:03 +00:00
gmcgarry
3647e0d293 Merge cpu_sysctl() for all mips ports, based on powerpc and m68k precedent. 
For now, only pmax implements CPU_BOOTED_KERNEL.  Need to revisit.
 2002-08-04 01:41:23 +00:00
gmcgarry
e0590ef08b Boot loader is now case sensitive. Fixes PR-17711. 2002-08-04 00:44:58 +00:00
thorpej
3b50c1710c * Define the 8-input, 16-input, and 32-input descriptors. 
* Adjust descriptor sync'ing to work with the additional descriptor
  formats.
 2002-08-03 21:58:55 +00:00
thorpej
a39c3378b6 Restructure the iopaau_function slightly to provide greater 
flexibility when using different descriptor formats.
 2002-08-03 21:31:16 +00:00
itojun
b41a39617e comment things out for smaller footprint 2002-08-03 15:52:20 +00:00
simonb
7cfa7d3ce0 Sprinkle a small amount of KNF. 2002-08-03 13:12:44 +00:00
isaki
2450cd0acc Fix compile warnings in debug code. 2002-08-03 06:38:41 +00:00
itojun
8dd04cdcd7 correct range check, have overflow check, fix type mismatches, 
for cmap args and some other calls.  from openbsd
 2002-08-03 00:12:48 +00:00
soren
8e607cdca8 G/c vestiges of old sun3-specific SYMTAB_SPACE support. 2002-08-02 18:19:58 +00:00
thorpej
c070073d8e Add support for xor2, xor3, and xor4. Fix inverted direction 
indications in some bus_dma operations.
 2002-08-02 06:52:16 +00:00
ichiro
2543e04449 chenge comment for wi(4) 
- add vender Intersil
 2002-08-02 05:26:44 +00:00
chs
810cde53cc use a completely separate trap handler for syscall traps. 
this reduces syscall overhead by 10% to 20% depending on cpu type.
 2002-08-02 03:46:42 +00:00
thorpej
58983a92ba Let the "zero" and "fill8" functions share a bunch of code. 2002-08-02 02:08:11 +00:00
thorpej
f7328ddbe7 Add dmoverio. 2002-08-02 00:50:25 +00:00
thorpej
6f79106887 Add dmoverio. 2002-08-02 00:45:37 +00:00